baytrail: Switch graphics init to use reg_script
This is an example consumer of the register script handler. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi and see recovery screen Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175214 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4924 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie
Aaron Durbin
parent
6e8c2790bb
commit
223d4a4ff6
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@ -23,186 +23,14 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <reg_script.h>
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#include <baytrail/gfx.h>
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#include <baytrail/iosf.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/ramstage.h>
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struct gt_reg {
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u32 reg;
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u32 andmask;
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u32 ormask;
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};
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static const struct gt_reg gfx_powermeter_weights[] = {
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/* SET1 */
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{ 0xA800, 0xFFFFFFFF, 0x00000000 },
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{ 0xA804, 0xFFFFFFFF, 0x00000000 },
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{ 0xA808, 0xFFFFFFFF, 0x0000ff0A },
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{ 0xA80C, 0xFFFFFFFF, 0x1D000000 },
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{ 0xA810, 0xFFFFFFFF, 0xAC004900 },
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{ 0xA814, 0xFFFFFFFF, 0x000F0000 },
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{ 0xA818, 0xFFFFFFFF, 0x5A000000 },
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{ 0xA81C, 0xFFFFFFFF, 0x2600001F },
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{ 0xA820, 0xFFFFFFFF, 0x00090000 },
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{ 0xA824, 0xFFFFFFFF, 0x2000ff00 },
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{ 0xA828, 0xFFFFFFFF, 0xff090016 },
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{ 0xA82C, 0xFFFFFFFF, 0x00000000 },
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{ 0xA830, 0xFFFFFFFF, 0x00000100 },
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{ 0xA834, 0xFFFFFFFF, 0x00A00F51 },
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{ 0xA838, 0xFFFFFFFF, 0x000B0000 },
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{ 0xA83C, 0xFFFFFFFF, 0xcb7D3307 },
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{ 0xA840, 0xFFFFFFFF, 0x003C0000 },
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{ 0xA844, 0xFFFFFFFF, 0xFFFF0000 },
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{ 0xA848, 0xFFFFFFFF, 0x00220000 },
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{ 0xA84c, 0xFFFFFFFF, 0x43000000 },
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{ 0xA850, 0xFFFFFFFF, 0x00000800 },
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{ 0xA854, 0xFFFFFFFF, 0x00000F00 },
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{ 0xA858, 0xFFFFFFFF, 0x00000021 },
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{ 0xA85c, 0xFFFFFFFF, 0x00000000 },
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{ 0xA860, 0xFFFFFFFF, 0x00190000 },
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{ 0xAA80, 0xFFFFFFFF, 0x00FF00FF },
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{ 0xAA84, 0xFFFFFFFF, 0x00000000 },
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{ 0x1300A4, 0xFFFFFFFF, 0x00000000 },
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/* SET2 */
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{ 0xA900, 0xFFFFFFFF, 0x00000000 },
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{ 0xA904, 0xFFFFFFFF, 0x00000000 },
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{ 0xA908, 0xFFFFFFFF, 0x00000000 },
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{ 0xa90c, 0xFFFFFFFF, 0x1D000000 },
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{ 0xa910, 0xFFFFFFFF, 0xAC005000 },
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{ 0xa914, 0xFFFFFFFF, 0x000F0000 },
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{ 0xa918, 0xFFFFFFFF, 0x5A000000 },
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{ 0xa91c, 0xFFFFFFFF, 0x2600001F },
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{ 0xa920, 0xFFFFFFFF, 0x00090000 },
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{ 0xa924, 0xFFFFFFFF, 0x2000ff00 },
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{ 0xa928, 0xFFFFFFFF, 0xff090016 },
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{ 0xa92c, 0xFFFFFFFF, 0x00000000 },
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{ 0xa930, 0xFFFFFFFF, 0x00000100 },
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{ 0xa934, 0xFFFFFFFF, 0x00A00F51 },
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{ 0xa938, 0xFFFFFFFF, 0x000B0000 },
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{ 0xA93C, 0xFFFFFFFF, 0xcb7D3307 },
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{ 0xA940, 0xFFFFFFFF, 0x003C0000 },
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{ 0xA944, 0xFFFFFFFF, 0xFFFF0000 },
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{ 0xA948, 0xFFFFFFFF, 0x00220000 },
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{ 0xA94C, 0xFFFFFFFF, 0x43000000 },
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{ 0xA950, 0xFFFFFFFF, 0x00000800 },
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{ 0xA954, 0xFFFFFFFF, 0x00000000 },
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{ 0xA960, 0xFFFFFFFF, 0x00000000 },
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/* SET3 */
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{ 0xaa3c, 0xFFFFFFFF, 0x00000000 },
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{ 0xaa54, 0xFFFFFFFF, 0x00000000 },
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{ 0xaa60, 0xFFFFFFFF, 0x00000000 },
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/* Enable PowerMeter Counters */
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{ 0xA248, 0xFFFFFFFF, 0x00000058 },
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{ 0 }
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};
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static const struct gt_reg gfx_rc6_registers[] = {
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{ 0xA090, 0xFFFFFFFF, 0x00000000 },
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/* RC1e - RC6/6p - RC6pp Wake Rate Limits */
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{ 0xA09C, 0xFFFFFFFF, 0x00280000 },
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{ 0xA0A8, 0xFFFFFFFF, 0x0001E848 },
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{ 0xA0AC, 0xFFFFFFFF, 0x00000019 },
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/* RC Sleep / RCx Thresholds */
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{ 0xA0B0, 0xFFFFFFFF, 0x00000000 },
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{ 0xA0B8, 0xFFFFFFFF, 0x00000557 },
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{ 0 }
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};
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static const struct gt_reg gfx_turbo_registers[] = {
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/* Render/Video/Blitter Idle Max Count */
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{ 0x2054, 0xFFFFFFFF, 0x0000000A },
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{ 0x12054, 0xFFFFFFFF, 0x0000000A },
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{ 0x22054, 0xFFFFFFFF, 0x0000000A },
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/* RP Down Timeout */
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{ 0xA010, 0xFFFFFFFF, 0x000F4240 },
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{ 0 }
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};
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static const struct gt_reg gfx_turbo_ctl_registers[] = {
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/* RP Up/Down Threshold */
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{ 0xA02C, 0xFFFFFFFF, 0x0000E8E8 },
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{ 0xA030, 0xFFFFFFFF, 0x0003BD08 },
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/* RP Up/Down EI */
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{ 0xA068, 0xFFFFFFFF, 0x000101D0 },
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{ 0xA06C, 0xFFFFFFFF, 0x00055730 },
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{ 0 }
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};
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static struct resource *gtt_res = NULL;
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static inline unsigned long gtt_read(unsigned long reg)
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{
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u32 val;
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val = read32(gtt_res->base + reg);
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return val;
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}
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static inline void gtt_write(unsigned long reg, unsigned long data)
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{
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write32(gtt_res->base + reg, data);
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}
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static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
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{
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u32 val = gtt_read(reg);
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val &= andmask;
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val |= ormask;
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gtt_write(reg, val);
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}
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static void gtt_write_regs(const struct gt_reg *gt)
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{
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for (; gt && gt->reg; gt++)
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gtt_rmw(gt->reg, gt->andmask, gt->ormask);
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}
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#define GFX_POLL_RETRY 10000
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static int gtt_poll(u32 reg, u32 mask, u32 value)
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{
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unsigned try = GFX_POLL_RETRY;
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u32 data;
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while (try--) {
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data = gtt_read(reg);
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if ((data & mask) == value)
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return 1;
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udelay(100);
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}
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printk(BIOS_ERR, "GTT timeout\n");
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return 0;
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}
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static int gfx_poll_power_gate(u32 mask, u32 value)
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{
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unsigned try = GFX_POLL_RETRY;
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u32 data;
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while (try--) {
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data = iosf_punit_read(PUNIT_PWRGT_STATUS);
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if ((data & mask) == value)
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return 1;
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udelay(100);
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}
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printk(BIOS_ERR, "Power Gate timeout\n");
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return 0;
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}
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#define GFX_TIMEOUT 100000 /* 100ms */
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/*
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* Lock Power Context Base Register to point to a 24KB block
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@ -210,6 +38,7 @@ static int gfx_poll_power_gate(u32 mask, u32 value)
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*/
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static void gfx_lock_pcbase(device_t dev)
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{
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256,
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288,320,352,384,416,448,480,512 };
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u32 pcsize = 24 << 10; /* 24KB */
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@ -227,154 +56,244 @@ static void gfx_lock_pcbase(device_t dev)
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pcbase += (gmsize-1) * wopcmsz - pcsize;
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pcbase |= 1; /* Lock */
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gtt_write(0x182120, pcbase);
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write32(res->base + 0x182120, pcbase);
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}
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static const struct reg_script gfx_init_script[] = {
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/* Allow-Wake render/media wells */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT),
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/* Render Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000,
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GFX_TIMEOUT),
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/* Media Force-Wake */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000),
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REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000,
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GFX_TIMEOUT),
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/* Workaround - X0:261954/A0:261955 */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1),
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/*
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* PowerMeter Weights
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*/
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/* SET1 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000),
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/* SET2 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000),
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/* SET3 */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000),
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/* Enable PowerMeter Counters */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058),
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/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
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/* SDP Profile 4 == 0x11940, others 0xcf08 */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
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/* GfxPause */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),
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/* Dynamic EU Control Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004),
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/* Lock ECO Bit Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000),
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/* DOP Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001),
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/* MBCunit will send the VCR (Fuse) writes as NP-W */
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REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000),
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/*
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* RC6 Settings
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*/
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000),
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/* RC1e - RC6/6p - RC6pp Wake Rate Limits */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019),
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/* RC Sleep / RCx Thresholds */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557),
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/*
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* Turbo Settings
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*/
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/* Render/Video/Blitter Idle Max Count */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A),
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/* RP Down Timeout */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240),
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/*
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* Turbo Control Settings
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*/
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/* RP Up/Down Threshold */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08),
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/* RP Up/Down EI */
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0),
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REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730),
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/* RP Idle Hysteresis */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a),
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/* HW RC6 Control Settings */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000),
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/* RP Control */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592),
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/* Enable PM Interrupts */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e),
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/* Aggressive Clock Gating */
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0),
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REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0),
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REG_SCRIPT_END
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};
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static const struct reg_script gpu_pre_vbios_script[] = {
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/* Make sure GFX is bus master with MMIO access */
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REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY),
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/* Display */
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REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0),
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REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0,
|
||||
GFX_TIMEOUT),
|
||||
/* Tx/Rx Lanes */
|
||||
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0),
|
||||
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0,
|
||||
GFX_TIMEOUT),
|
||||
/* Common Lane */
|
||||
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0),
|
||||
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0,
|
||||
GFX_TIMEOUT),
|
||||
/* Ungating Tx only */
|
||||
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0),
|
||||
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0,
|
||||
GFX_TIMEOUT),
|
||||
/* Ungating Common Lane only */
|
||||
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0),
|
||||
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0,
|
||||
GFX_TIMEOUT),
|
||||
/* Ungating Display */
|
||||
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000),
|
||||
REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000,
|
||||
GFX_TIMEOUT),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static const struct reg_script gfx_post_vbios_script[] = {
|
||||
/* Deassert Render Force-Wake */
|
||||
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000),
|
||||
REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT),
|
||||
/* Deassert Media Force-Wake */
|
||||
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000),
|
||||
REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT),
|
||||
/* Set Lock bits */
|
||||
REG_PCI_RMW32(GGC, 0xffffffff, 1),
|
||||
REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1),
|
||||
REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1),
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
static void gfx_run_script(device_t dev, const struct reg_script *ops)
|
||||
{
|
||||
struct reg_script steps[] = {
|
||||
REG_SCRIPT_SET_DEV(dev),
|
||||
REG_SCRIPT_NEXT(ops),
|
||||
REG_SCRIPT_END,
|
||||
};
|
||||
reg_script_run(&steps[0]);
|
||||
}
|
||||
|
||||
static void gfx_pre_vbios_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
|
||||
gfx_run_script(dev, gpu_pre_vbios_script);
|
||||
}
|
||||
|
||||
static void gfx_pm_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_INFO, "GFX: Power Management Init\n");
|
||||
|
||||
/*
|
||||
* Allow-Wake render/media wells.
|
||||
* Used by PUNIT as part of S0IX save/restore.
|
||||
*/
|
||||
gtt_rmw(0x130090, ~1, 1);
|
||||
if (!gtt_poll(0x130094, 1, 1)) {
|
||||
printk(BIOS_ERR, "gfx_pm_init: Unable to allow-wake\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Render Force-Wake */
|
||||
gtt_write(0x1300B0, 0x80008000);
|
||||
if (!gtt_poll(0x1300B4, 0x8000, 0x8000)) {
|
||||
printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake render\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Media Force-Wake */
|
||||
gtt_write(0x1300B8, 0x80008000);
|
||||
if (!gtt_poll(0x1300BC, 0x8000, 0x8000)) {
|
||||
printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake media\n");
|
||||
return;
|
||||
};
|
||||
|
||||
/* Workaround - X0:261954/A0:261955 */
|
||||
gtt_rmw(0x182060, ~0xf, 1);
|
||||
|
||||
/* Program GT PowerMeter weights */
|
||||
gtt_write_regs(gfx_powermeter_weights);
|
||||
|
||||
/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
|
||||
/* SDP Profile 4 == 0x11940, others 0xcf08 */
|
||||
iosf_punit_write(PUNIT_GPU_EC_VIRUS, 0xcf08);
|
||||
|
||||
/* GfxPause */
|
||||
gtt_write(0xa000, 0x00071388);
|
||||
|
||||
/* Dynamic EU Control Settings */
|
||||
gtt_write(0xa080, 0x00000004);
|
||||
|
||||
/* Lock ECO Bit Settings */
|
||||
gtt_write(0xa180, 0x80000000);
|
||||
|
||||
/* DOP Clock Gating */
|
||||
gtt_write(0x9424, 0x00000001);
|
||||
|
||||
/* MBCunit will send the VCR (Fuse) writes as NP-W */
|
||||
gtt_rmw(0x907c, 0xfffeffff, 0x00010000);
|
||||
|
||||
/* RC6 Settings */
|
||||
gtt_write_regs(gfx_rc6_registers);
|
||||
|
||||
/* Turbo Settings */
|
||||
gtt_write_regs(gfx_turbo_registers);
|
||||
|
||||
/* Turbo Control Settings */
|
||||
gtt_write_regs(gfx_turbo_ctl_registers);
|
||||
|
||||
/* RP Idle Hysteresis */
|
||||
gtt_write(0xa070, 0x0000000a);
|
||||
|
||||
/* HW RC6 Control Settings */
|
||||
gtt_write(0xa090, 0x11000000);
|
||||
|
||||
/* RP Control */
|
||||
gtt_write(0xa024, 0x00000592);
|
||||
|
||||
/* Enable PM Interrupts */
|
||||
gtt_write(0x44024, 0x03000000);
|
||||
gtt_write(0x4402c, 0x03000076);
|
||||
gtt_write(0xa168, 0x0000007e);
|
||||
gfx_run_script(dev, gfx_init_script);
|
||||
|
||||
/* Lock power context base */
|
||||
gfx_lock_pcbase(dev);
|
||||
|
||||
/* Aggressive Clock Gating */
|
||||
gtt_write(0x9400, 0);
|
||||
gtt_write(0x9404, 0);
|
||||
gtt_write(0x9408, 0);
|
||||
gtt_write(0x940c, 0);
|
||||
}
|
||||
|
||||
static void gfx_pre_vbios_init(device_t dev)
|
||||
{
|
||||
/* Display */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xc0);
|
||||
gfx_poll_power_gate(0xc0, 0xc0);
|
||||
|
||||
/* Tx/Rx Lanes */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfff0c0);
|
||||
gfx_poll_power_gate(0xfff0c0, 0xfff0c0);
|
||||
|
||||
/* Common Lane */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfffcc0);
|
||||
gfx_poll_power_gate(0xfffcc0, 0xfffcc0);
|
||||
|
||||
/* Ungating Tx only */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00cc0);
|
||||
gfx_poll_power_gate(0xfffcc0, 0xf00cc0);
|
||||
|
||||
/* Ungating Common Lane only */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf000c0);
|
||||
gfx_poll_power_gate(0xffffc0, 0xf000c0);
|
||||
|
||||
/* Ungating Display */
|
||||
iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00000);
|
||||
gfx_poll_power_gate(0xfffff0, 0xf00000);
|
||||
}
|
||||
|
||||
static void gfx_post_vbios_init(device_t dev)
|
||||
{
|
||||
/* Deassert Render Force-Wake */
|
||||
gtt_write(0x1300B0, 0x80000000);
|
||||
gtt_poll(0x1300B4, 0x8000, 0);
|
||||
|
||||
/* Deassert Media Force-Wake */
|
||||
gtt_write(0x1300B8, 0x80000000);
|
||||
gtt_poll(0x1300BC, 0x8000, 0);
|
||||
|
||||
/* Set Lock bits */
|
||||
pci_write_config32(dev, GGC, pci_read_config32(dev, GGC) | 1);
|
||||
pci_write_config32(dev, GSM_BASE, pci_read_config32(dev, GSM_BASE) | 1);
|
||||
pci_write_config32(dev, GTT_BASE, pci_read_config32(dev, GTT_BASE) | 1);
|
||||
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
|
||||
gfx_run_script(dev, gfx_post_vbios_script);
|
||||
}
|
||||
|
||||
static void gfx_init(device_t dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Find GTT resource */
|
||||
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (!gtt_res || !gtt_res->base)
|
||||
return;
|
||||
|
||||
/* GFX needs to be Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32);
|
||||
|
||||
/* Pre VBIOS Init */
|
||||
gfx_pre_vbios_init(dev);
|
||||
|
||||
/* Power Management Init */
|
||||
gfx_pm_init(dev);
|
||||
|
||||
/* Run VBIOS */
|
||||
|
|
|
|||
Loading…
Reference in New Issue