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mb/google/deltaur: Add support to enable GbE on variant 

- Configure devicetree for enabling GbE on variant
  and remove from baseboard.
- Configure Kconfig to enable GbE region.
- Configure fmd to incorporate GbE.

BUG=b:151102809
Cq-Depend: chrome-internal:2843183
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I1c36b132546049e3e775585c41164072f4ece73e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Varun Joshi 2020-03-31 18:02:33 -07:00 committed by Martin Roth
parent c6f5b05cf3
commit 2255ebaa23
4 changed files with 20 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/deltaur/Kconfig
View File

@ -15,6 +15,7 @@ config BOARD_GOOGLE_BASEBOARD_DELTAUR
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_TIGERLAKE
select SYSTEM_TYPE_LAPTOP
select MAINBOARD_USES_IFD_GBE_REGION if BOARD_GOOGLE_DELTAN
if BOARD_GOOGLE_BASEBOARD_DELTAUR

23
src/mainboard/google/deltaur/chromeos.fmd
View File

@ -1,26 +1,27 @@
FLASH@0xfe000000 0x2000000 {
SI_ALL@0x0 0x604000 {
SI_ALL@0x0 0x606000 {
SI_DESC@0x0 0x1000
SI_EC@0x1000 0x100000
SI_ME@0x101000 0x4ff000
SI_PDR(PRESERVE)@0x600000 0x4000
SI_GBE(PRESERVE)@0x101000 0x2000
SI_ME@0x103000 0x4ff000
SI_PDR(PRESERVE)@0x602000 0x4000
}
SI_BIOS@0x604000 0x19fc000 {
RW_DIAG@0x0 0x10cc000 {
RW_LEGACY(CBFS)@0x0 0x10bc000
DIAG_NVRAM@0x10bc000 0x10000
SI_BIOS@0x606000 0x19fa000 {
RW_DIAG@0x0 0x10ca000 {
RW_LEGACY(CBFS)@0x0 0x10ba000
DIAG_NVRAM@0x10ba000 0x10000
}
RW_SECTION_A@0x10cc000 0x280000 {
RW_SECTION_A@0x10ca000 0x280000 {
VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x26ffc0
RW_FWID_A@0x27ffc0 0x40
}
RW_SECTION_B@0x134c000 0x280000 {
RW_SECTION_B@0x134a000 0x280000 {
VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x26ffc0
RW_FWID_B@0x27ffc0 0x40
}
RW_MISC@0x15cc000 0x30000 {
RW_MISC@0x15ca000 0x30000 {
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
@ -33,7 +34,7 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
WP_RO@0x15fc000 0x400000 {
WP_RO@0x15fa000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_UNUSED@0x4000 0xc000
RO_SECTION@0x10000 0x3f0000 {

7
src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
View File

@ -59,11 +59,6 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[4]" = "6"
register "PcieClkSrcClkReq[4]" = "4"
# PCIe port root 8 (LAN), clock 3
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[3]" = "3"
# PCIe root port 9 (NVMe), clock 2
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcUsage[2]" = "8"
@ -332,7 +327,7 @@ chip soc/intel/tigerlake
device pci 1f.3 on end # Intel HDA
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI Flash Controller
device pci 1f.6 on end # GbE Controller
device pci 1f.6 off end # GbE Controller
device pci 1f.7 off end # Intel Trace Hub
end
end

6
src/mainboard/google/deltaur/variants/deltan/overridetree.cb
View File

@ -1,6 +1,12 @@
chip soc/intel/tigerlake
# PCIe Port 8 for LAN
register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
register "PcieClkSrcClkReq[3]" = "3"
device domain 0 on
device pci 1f.6 on end # GbE 0x15FC
end
end