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mb/google/octopus: Fix GPIO config for DRAM_IDs 

The GPIO pad configurations for GPIO68-71 are incorrectly configured as
outputs. This change corrects them to be inputs.

BUG=b:74932341
TEST=None

Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25217
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Justin TerAvest 2018-03-15 16:28:57 -06:00 committed by Martin Roth
parent 04ccd5f9b5
commit 22595f6e45
1 changed files with 4 additions and 4 deletions
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8
src/mainboard/google/octopus/variants/baseboard/gpio.c
View File

@ -92,10 +92,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS0 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS1 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_FS2 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_RXD */
PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */
PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_TXD */
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* PMC_SPI_CLK */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */