soc/amd/stoneyridge: Fix smi_write32 arg order in disable_all_smi_status
The argument order for smi_write32() is offset, value. Current code had it backwards. So, when disable_all_smi_status() was called by sb_slp_typ_handler(), instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2 by writing 0x00000002 to 0xfed80288, it would instead write 0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04 Event_Enable, which disabled the lower 16 GPEs from waking the system from S3. Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7] did not work as wake up sources. BUG=b:78461678 TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3. Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46 Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler") Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -112,12 +112,12 @@ static void sb_apmc_smi_handler(void)
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static void disable_all_smi_status(void)
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{
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smi_write32(smi_read32(SMI_SCI_STATUS), SMI_SCI_STATUS);
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smi_write32(smi_read32(SMI_REG_SMISTS0), SMI_REG_SMISTS0);
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smi_write32(smi_read32(SMI_REG_SMISTS1), SMI_REG_SMISTS1);
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smi_write32(smi_read32(SMI_REG_SMISTS2), SMI_REG_SMISTS2);
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smi_write32(smi_read32(SMI_REG_SMISTS3), SMI_REG_SMISTS3);
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smi_write32(smi_read32(SMI_REG_SMISTS4), SMI_REG_SMISTS4);
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smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS));
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smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0));
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smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1));
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smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2));
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smi_write32(SMI_REG_SMISTS3, smi_read32(SMI_REG_SMISTS3));
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smi_write32(SMI_REG_SMISTS4, smi_read32(SMI_REG_SMISTS4));
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}
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static void sb_slp_typ_handler(void)
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