diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 990e10607b..ea956a70f1 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -1418,12 +1418,28 @@ void cse_late_finalize(void)
 		cse_final_end_of_firmware();
 }
 
+static void intel_cse_get_rw_version(void)
+{
+	struct cse_fw_partition_info *version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION);
+	if (version == NULL)
+		return;
+
+	printk(BIOS_DEBUG, "CSE RW Firmware Version: %d.%d.%d.%d\n",
+		version->cur_cse_fw_version.major,
+		version->cur_cse_fw_version.minor,
+		version->cur_cse_fw_version.hotfix,
+		version->cur_cse_fw_version.build);
+}
+
 /*
  * `cse_final` function is native implementation of equivalent events performed by
- * each FSP NotifyPhase() API invocations.
+ * each FSP NotifyPhase() API invocations. It also displays CSE firmware version
+ * if stored in CBMEM region.
  */
 static void cse_final(struct device *dev)
 {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
+		intel_cse_get_rw_version();
 	/*
 	 * SoC user can have two options for sending EOP:
 	 * 1. Choose to send EOP late