AGESA fam10 fam12 fam15: Always have HT3_SUPPORT
Keep the slower HyperTransport configuration for a possible reference in fam15 boards. Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
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}
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}
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};
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};
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#if CONFIG_HT3_SUPPORT
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#define HYPERTRANSPORT_V31_SUPPORT 1
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#if HYPERTRANSPORT_V31_SUPPORT
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/**
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/**
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* The socket and link match values are platform specific
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* The socket and link match values are platform specific
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*
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*
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@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
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HT_LIST_TERMINAL,
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HT_LIST_TERMINAL,
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}
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}
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};
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};
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#else //CONFIG_HT3_SUPPORT == 0
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#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
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{
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{
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{
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{
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@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
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HT_LIST_TERMINAL
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HT_LIST_TERMINAL
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}
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}
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};
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};
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#endif //CONFIG_HT3_SUPPORT == 0
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#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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/**
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/**
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* HyperTransport links will typically require an equalization at high frequencies.
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* HyperTransport links will typically require an equalization at high frequencies.
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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] =
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}
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}
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};
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};
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#if CONFIG_HT3_SUPPORT
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#define HYPERTRANSPORT_V31_SUPPORT 1
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#if HYPERTRANSPORT_V31_SUPPORT
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/**
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/**
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* The socket and link match values are platform specific
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* The socket and link match values are platform specific
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*
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*
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@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
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HT_LIST_TERMINAL,
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HT_LIST_TERMINAL,
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}
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}
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};
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};
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#else //CONFIG_HT3_SUPPORT == 0
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#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] =
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] =
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{
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{
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{
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{
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@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
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HT_LIST_TERMINAL
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HT_LIST_TERMINAL
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}
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}
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};
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};
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#endif //CONFIG_HT3_SUPPORT == 0
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#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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/**
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/**
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* HyperTransport links will typically require an equalization at high frequencies.
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* HyperTransport links will typically require an equalization at high frequencies.
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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
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}
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}
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};
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};
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#if CONFIG_HT3_SUPPORT
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#define HYPERTRANSPORT_V31_SUPPORT 1
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#if HYPERTRANSPORT_V31_SUPPORT
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/**
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/**
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* The socket and link match values are platform specific
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* The socket and link match values are platform specific
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*
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*
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@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
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HT_LIST_TERMINAL,
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HT_LIST_TERMINAL,
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}
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}
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};
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};
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#else //CONFIG_HT3_SUPPORT == 0
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#else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
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CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
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{
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{
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{
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{
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@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
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HT_LIST_TERMINAL
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HT_LIST_TERMINAL
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}
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}
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};
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};
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#endif //CONFIG_HT3_SUPPORT == 0
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#endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
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/**
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/**
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* HyperTransport links will typically require an equalization at high frequencies.
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* HyperTransport links will typically require an equalization at high frequencies.
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@ -25,19 +25,21 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT
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if NORTHBRIDGE_AMD_AGESA_FAMILY10
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if NORTHBRIDGE_AMD_AGESA_FAMILY10
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config HT3_SUPPORT
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bool
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default y
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config HW_MEM_HOLE_SIZEK
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config HW_MEM_HOLE_SIZEK
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hex
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hex
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default 0x100000
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default 0x100000
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config HW_MEM_HOLE_SIZE_AUTO_INC
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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bool
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default n
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default n
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config MMCONF_BASE_ADDRESS
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config MMCONF_BASE_ADDRESS
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hex
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hex
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default 0xE0000000
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default 0xE0000000
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config MMCONF_BUS_NUMBER
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config MMCONF_BUS_NUMBER
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int
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int
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default 256
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default 256
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endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
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endif #NORTHBRIDGE_AMD_AGESA_FAMILY10
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@ -1133,13 +1133,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
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/* Ok, We need to set the links for that device.
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/* Ok, We need to set the links for that device.
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* otherwise the device under it will not be scanned
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* otherwise the device under it will not be scanned
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*/
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*/
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int linknum;
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add_more_links(cdb_dev, 8);
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#if CONFIG_HT3_SUPPORT
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linknum = 8;
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#else
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linknum = 4;
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#endif
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add_more_links(cdb_dev, linknum);
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}
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}
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cores_found = 0; // one core
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cores_found = 0; // one core
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@ -26,10 +26,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12
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if NORTHBRIDGE_AMD_AGESA_FAMILY12
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if NORTHBRIDGE_AMD_AGESA_FAMILY12
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config HT3_SUPPORT
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bool
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default y
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config HW_MEM_HOLE_SIZEK
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config HW_MEM_HOLE_SIZEK
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hex
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hex
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default 0x100000
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default 0x100000
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@ -26,9 +26,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15
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select PER_DEVICE_ACPI_TABLES
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select PER_DEVICE_ACPI_TABLES
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if NORTHBRIDGE_AMD_AGESA_FAMILY15
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if NORTHBRIDGE_AMD_AGESA_FAMILY15
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config HT3_SUPPORT
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bool
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default y
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config HW_MEM_HOLE_SIZEK
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config HW_MEM_HOLE_SIZEK
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hex
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hex
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default 0x100000
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default 0x100000
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@ -1131,13 +1131,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
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/* Ok, We need to set the links for that device.
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/* Ok, We need to set the links for that device.
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* otherwise the device under it will not be scanned
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* otherwise the device under it will not be scanned
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*/
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*/
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int linknum;
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add_more_links(cdb_dev, 8);
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#if CONFIG_HT3_SUPPORT
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linknum = 8;
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#else
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linknum = 4;
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#endif
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add_more_links(cdb_dev, linknum);
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}
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}
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family = cpuid_eax(1);
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family = cpuid_eax(1);
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