AGESA fam10 fam12 fam15: Always have HT3_SUPPORT

Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.

Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kyösti Mälkki 2015-02-04 13:46:12 +02:00
parent ddea94259a
commit 225da645ad
8 changed files with 23 additions and 33 deletions

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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
} }
}; };
#if CONFIG_HT3_SUPPORT #define HYPERTRANSPORT_V31_SUPPORT 1
#if HYPERTRANSPORT_V31_SUPPORT
/** /**
* The socket and link match values are platform specific * The socket and link match values are platform specific
* *
@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
HT_LIST_TERMINAL, HT_LIST_TERMINAL,
} }
}; };
#else //CONFIG_HT3_SUPPORT == 0 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] = CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8qgi_cpu2cpu_limit_list[2] =
{ {
{ {
@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8qgi_io_limit_list[2] =
HT_LIST_TERMINAL HT_LIST_TERMINAL
} }
}; };
#endif //CONFIG_HT3_SUPPORT == 0 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
/** /**
* HyperTransport links will typically require an equalization at high frequencies. * HyperTransport links will typically require an equalization at high frequencies.

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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] =
} }
}; };
#if CONFIG_HT3_SUPPORT #define HYPERTRANSPORT_V31_SUPPORT 1
#if HYPERTRANSPORT_V31_SUPPORT
/** /**
* The socket and link match values are platform specific * The socket and link match values are platform specific
* *
@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
HT_LIST_TERMINAL, HT_LIST_TERMINAL,
} }
}; };
#else //CONFIG_HT3_SUPPORT == 0 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] =
{ {
{ {
@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] =
HT_LIST_TERMINAL HT_LIST_TERMINAL
} }
}; };
#endif //CONFIG_HT3_SUPPORT == 0 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
/** /**
* HyperTransport links will typically require an equalization at high frequencies. * HyperTransport links will typically require an equalization at high frequencies.

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@ -204,7 +204,9 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
} }
}; };
#if CONFIG_HT3_SUPPORT #define HYPERTRANSPORT_V31_SUPPORT 1
#if HYPERTRANSPORT_V31_SUPPORT
/** /**
* The socket and link match values are platform specific * The socket and link match values are platform specific
* *
@ -240,7 +242,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
HT_LIST_TERMINAL, HT_LIST_TERMINAL,
} }
}; };
#else //CONFIG_HT3_SUPPORT == 0 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] = CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
{ {
{ {
@ -272,7 +274,7 @@ CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
HT_LIST_TERMINAL HT_LIST_TERMINAL
} }
}; };
#endif //CONFIG_HT3_SUPPORT == 0 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
/** /**
* HyperTransport links will typically require an equalization at high frequencies. * HyperTransport links will typically require an equalization at high frequencies.

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@ -25,19 +25,21 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY10
select MMCONF_SUPPORT select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_AGESA_FAMILY10 if NORTHBRIDGE_AMD_AGESA_FAMILY10
config HT3_SUPPORT
bool
default y
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0x100000 default 0x100000
config HW_MEM_HOLE_SIZE_AUTO_INC config HW_MEM_HOLE_SIZE_AUTO_INC
bool bool
default n default n
config MMCONF_BASE_ADDRESS config MMCONF_BASE_ADDRESS
hex hex
default 0xE0000000 default 0xE0000000
config MMCONF_BUS_NUMBER config MMCONF_BUS_NUMBER
int int
default 256 default 256
endif #NORTHBRIDGE_AMD_AGESA_FAMILY10 endif #NORTHBRIDGE_AMD_AGESA_FAMILY10

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@ -1133,13 +1133,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
/* Ok, We need to set the links for that device. /* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned * otherwise the device under it will not be scanned
*/ */
int linknum; add_more_links(cdb_dev, 8);
#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
#endif
add_more_links(cdb_dev, linknum);
} }
cores_found = 0; // one core cores_found = 0; // one core

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@ -26,10 +26,6 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY12
if NORTHBRIDGE_AMD_AGESA_FAMILY12 if NORTHBRIDGE_AMD_AGESA_FAMILY12
config HT3_SUPPORT
bool
default y
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0x100000 default 0x100000

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@ -26,9 +26,7 @@ config NORTHBRIDGE_AMD_AGESA_FAMILY15
select PER_DEVICE_ACPI_TABLES select PER_DEVICE_ACPI_TABLES
if NORTHBRIDGE_AMD_AGESA_FAMILY15 if NORTHBRIDGE_AMD_AGESA_FAMILY15
config HT3_SUPPORT
bool
default y
config HW_MEM_HOLE_SIZEK config HW_MEM_HOLE_SIZEK
hex hex
default 0x100000 default 0x100000

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@ -1131,13 +1131,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
/* Ok, We need to set the links for that device. /* Ok, We need to set the links for that device.
* otherwise the device under it will not be scanned * otherwise the device under it will not be scanned
*/ */
int linknum; add_more_links(cdb_dev, 8);
#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
#endif
add_more_links(cdb_dev, linknum);
} }
family = cpuid_eax(1); family = cpuid_eax(1);