vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3172

The headers added are generated as per FSP v3172

In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.

BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I5aa0611b19bb4f6667a95d2539cc2d17de6dcf07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/vendorcode/intel/fsp/fsp2_0/raptorlake/FirmwareVersionInfoHob.h

@@ -65,4 +65,4 @@ typedef struct {
 } FIRMWARE_VERSION_INFO_HOB;
 #pragma pack()
 
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
+#endif // _FIRMWARE_VERSION_INFO_HOB_H_

src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h

@@ -47,10 +47,6 @@ extern EFI_GUID gSiMemoryPlatformDataGuid;
 #define MAX_NODE        2
 #define MAX_CH          4
 #define MAX_DIMM        2
-// SA:RestrictedBegin
-//   This should move to a public interface to share the same constant \ struct
-//   defintion between MRC and wrapper platform code.
-// SA:RestrictedEnd
 #define HOB_MAX_SAGV_POINTS 4
 
 ///
@@ -325,13 +321,6 @@ typedef struct {
   UINT32            GttBase;
   UINT32            MmioSize;
   UINT32            PciEBaseAddress;
-//
-// CPU:RestrictedBegin
-//
-  UINT32            SharedMailboxBase;
-//
-// CPU:RestrictedEnd
-//
   PSMI_MEM_INFO     PsmiInfo[MAX_TRACE_CACHE_TYPE];
   PSMI_MEM_INFO     PsmiRegionInfo[MAX_TRACE_REGION];
   BOOLEAN           MrcBasicMemoryTestPass;