soc/intel/cannonlake: Add support for all UART port index

Select LPSS UART Base address based on LPSS UART port index.

Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/include/soc/iomap.h

@@ -28,8 +28,12 @@
 
 #define PCH_TRACE_HUB_BASE_ADDRESS	0xfc800000
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
-#define UART_DEBUG_BASE_ADDRESS	0xfe036000
-#define UART_DEBUG_BASE_SIZE	0x1000
+
+#define UART_DEBUG_BASE_0_SIZE	0x1000
+#define UART_BASE_0_ADDRESS	0xfe032000
+/* Both UART BAR 0 and 1 are 4KB in size */
+#define UART_BASE_0_ADDR(x)	(UART_BASE_0_ADDRESS + (2 * \
+					UART_DEBUG_BASE_0_SIZE * (x)))
 
 #define EARLY_I2C_BASE_ADDRESS	0xfe040000
 #define EARLY_I2C_BASE(x)	(EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))

src/soc/intel/cannonlake/uart.c

@@ -79,6 +79,6 @@ void pch_uart_init(void)
 uintptr_t uart_platform_base(int idx)
 {
 	/* We can only have one serial console at a time */
-	return UART_DEBUG_BASE_ADDRESS;
+	return UART_BASE_0_ADDR(idx);
 }
 #endif