soc/intel/cannonlake: Add support for all UART port index
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -28,8 +28,12 @@
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#define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000
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#define PCH_TRACE_HUB_BASE_SIZE 0x00800000
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#define UART_DEBUG_BASE_ADDRESS 0xfe036000
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#define UART_DEBUG_BASE_SIZE 0x1000
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#define UART_DEBUG_BASE_0_SIZE 0x1000
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#define UART_BASE_0_ADDRESS 0xfe032000
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/* Both UART BAR 0 and 1 are 4KB in size */
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#define UART_BASE_0_ADDR(x) (UART_BASE_0_ADDRESS + (2 * \
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UART_DEBUG_BASE_0_SIZE * (x)))
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#define EARLY_I2C_BASE_ADDRESS 0xfe040000
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#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x)))
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@ -79,6 +79,6 @@ void pch_uart_init(void)
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uintptr_t uart_platform_base(int idx)
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{
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/* We can only have one serial console at a time */
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return UART_DEBUG_BASE_ADDRESS;
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return UART_BASE_0_ADDR(idx);
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}
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#endif
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