ibexpeak, bd82x6x: Move to implicit length patching
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Vladimir Serbinenko
parent
b1709bd0b2
commit
226d784377
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@ -48,10 +48,10 @@ static int get_cores_per_package(void)
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return cores;
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}
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static int generate_cstate_entries(acpi_cstate_t *cstates,
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static void generate_cstate_entries(acpi_cstate_t *cstates,
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int c1, int c2, int c3)
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{
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int length, cstate_count = 0;
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int cstate_count = 0;
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/* Count number of active C-states */
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if (c1 > 0)
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@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
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if (c3 > 0)
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++cstate_count;
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if (!cstate_count)
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return 0;
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return;
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length = acpigen_write_package(cstate_count + 1);
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length += acpigen_write_byte(cstate_count);
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acpigen_write_package(cstate_count + 1);
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acpigen_write_byte(cstate_count);
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/* Add an entry if the level is enabled */
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if (c1 > 0) {
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cstates[c1].ctype = 1;
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length += acpigen_write_CST_package_entry(&cstates[c1]);
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acpigen_write_CST_package_entry(&cstates[c1]);
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}
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if (c2 > 0) {
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cstates[c2].ctype = 2;
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length += acpigen_write_CST_package_entry(&cstates[c2]);
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acpigen_write_CST_package_entry(&cstates[c2]);
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}
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if (c3 > 0) {
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cstates[c3].ctype = 3;
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length += acpigen_write_CST_package_entry(&cstates[c3]);
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acpigen_write_CST_package_entry(&cstates[c3]);
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}
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acpigen_patch_len(length - 1);
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return length;
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acpigen_pop_len();
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}
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static int generate_C_state_entries(void)
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static void generate_C_state_entries(void)
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{
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struct cpu_info *info;
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struct cpu_driver *cpu;
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int len, lenif;
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struct device *lapic;
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struct cpu_intel_fsp_model_206ax_config *conf = NULL;
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/* Find the SpeedStep CPU in the device tree using magic APIC ID */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic)
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return 0;
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return;
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conf = lapic->chip_info;
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if (!conf)
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return 0;
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return;
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/* Find CPU map of supported C-states */
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info = cpu_info();
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if (!info)
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return 0;
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return;
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cpu = find_cpu_driver(info->cpu);
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if (!cpu || !cpu->cstates)
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return 0;
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return;
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len = acpigen_emit_byte(0x14); /* MethodOp */
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len += acpigen_write_len_f(); /* PkgLength */
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len += acpigen_emit_namestring("_CST");
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len += acpigen_emit_byte(0x00); /* No Arguments */
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acpigen_emit_byte(0x14); /* MethodOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("_CST");
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acpigen_emit_byte(0x00); /* No Arguments */
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/* If running on AC power */
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len += acpigen_emit_byte(0xa0); /* IfOp */
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lenif = acpigen_write_len_f(); /* PkgLength */
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lenif += acpigen_emit_namestring("PWRS");
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lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
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lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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acpigen_emit_byte(0xa0); /* IfOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("PWRS");
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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conf->c2_acpower, conf->c3_acpower);
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acpigen_patch_len(lenif - 1);
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len += lenif;
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acpigen_pop_len();
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/* Else on battery power */
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len += acpigen_emit_byte(0xa4); /* ReturnOp */
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len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_battery,
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conf->c2_battery, conf->c3_battery);
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acpigen_patch_len(len - 1);
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return len;
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acpigen_pop_len();
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}
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static acpi_tstate_t tss_table_fine[] = {
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@ -160,31 +156,27 @@ static acpi_tstate_t tss_table_coarse[] = {
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{ 13, 125, 0, 0x19, 0 },
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};
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static int generate_T_state_entries(int core, int cores_per_package)
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static void generate_T_state_entries(int core, int cores_per_package)
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{
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int len;
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/* Indicate SW_ALL coordination for T-states */
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len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
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/* Indicate FFixedHW so OS will use MSR */
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len += acpigen_write_empty_PTC();
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acpigen_write_empty_PTC();
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/* Set a T-state limit that can be modified in NVS */
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len += acpigen_write_TPC("\\TLVL");
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acpigen_write_TPC("\\TLVL");
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/*
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* CPUID.(EAX=6):EAX[5] indicates support
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* for extended throttle levels.
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*/
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if (cpuid_eax(6) & (1 << 5))
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len += acpigen_write_TSS_package(
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acpigen_write_TSS_package(
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ARRAY_SIZE(tss_table_fine), tss_table_fine);
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else
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len += acpigen_write_TSS_package(
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acpigen_write_TSS_package(
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ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
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return len;
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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@ -208,9 +200,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static int generate_P_state_entries(int core, int cores_per_package)
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static void generate_P_state_entries(int core, int cores_per_package)
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{
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int len, len_pss;
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, power_unit, num_entries;
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int ratio, power, clock, clock_max;
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@ -245,16 +236,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC_NVS();
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acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
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acpigen_write_PSD_package(core, cores_per_package, coord_type);
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/* Add P-state entries in _PSS table */
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len += acpigen_write_name("_PSS");
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acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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@ -267,13 +258,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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len_pss = acpigen_write_package(num_entries + 2);
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acpigen_write_package(num_entries + 2);
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msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
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ratio_turbo = msr.lo & 0xff;
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/* Add entry for Turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max + 1, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -282,11 +273,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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ratio_turbo << 8); /*status*/
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} else {
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/* _PSS package count without Turbo */
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len_pss = acpigen_write_package(num_entries + 1);
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acpigen_write_package(num_entries + 1);
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}
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/* First regular entry is max non-turbo ratio */
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock_max, /*MHz*/
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power_max, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -302,7 +293,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * SANDYBRIDGE_BCLK;
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len_pss += acpigen_write_PSS_package(
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acpigen_write_PSS_package(
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clock, /*MHz*/
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power, /*mW*/
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PSS_LATENCY_TRANSITION, /*lat1*/
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@ -312,15 +303,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
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}
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/* Fix package length */
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len_pss--;
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acpigen_patch_len(len_pss);
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return len + len_pss;
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acpigen_pop_len();
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}
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void generate_cpu_entries(void)
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{
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int len_pr;
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int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
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int totalcores = dev_count_cpu();
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int cores_per_package = get_cores_per_package();
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@ -337,23 +324,22 @@ void generate_cpu_entries(void)
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}
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/* Generate processor \_PR.CPUx */
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len_pr = acpigen_write_processor(
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acpigen_write_processor(
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(cpuID-1)*cores_per_package+coreID-1,
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pcontrol_blk, plen);
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/* Generate P-state tables */
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len_pr += generate_P_state_entries(
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generate_P_state_entries(
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cpuID-1, cores_per_package);
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/* Generate C-state tables */
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len_pr += generate_C_state_entries();
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generate_C_state_entries();
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/* Generate T-state tables */
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len_pr += generate_T_state_entries(
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generate_T_state_entries(
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cpuID-1, cores_per_package);
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len_pr--;
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acpigen_patch_len(len_pr);
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acpigen_pop_len();
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}
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}
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}
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@ -48,10 +48,10 @@ static int get_cores_per_package(void)
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return cores;
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}
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static int generate_cstate_entries(acpi_cstate_t *cstates,
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static void generate_cstate_entries(acpi_cstate_t *cstates,
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int c1, int c2, int c3)
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{
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int length, cstate_count = 0;
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int cstate_count = 0;
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/* Count number of active C-states */
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if (c1 > 0)
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@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
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if (c3 > 0)
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++cstate_count;
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if (!cstate_count)
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return 0;
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return;
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length = acpigen_write_package(cstate_count + 1);
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length += acpigen_write_byte(cstate_count);
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acpigen_write_package(cstate_count + 1);
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acpigen_write_byte(cstate_count);
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/* Add an entry if the level is enabled */
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if (c1 > 0) {
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cstates[c1].ctype = 1;
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length += acpigen_write_CST_package_entry(&cstates[c1]);
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acpigen_write_CST_package_entry(&cstates[c1]);
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}
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if (c2 > 0) {
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cstates[c2].ctype = 2;
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length += acpigen_write_CST_package_entry(&cstates[c2]);
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acpigen_write_CST_package_entry(&cstates[c2]);
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}
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if (c3 > 0) {
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cstates[c3].ctype = 3;
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length += acpigen_write_CST_package_entry(&cstates[c3]);
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acpigen_write_CST_package_entry(&cstates[c3]);
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}
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acpigen_patch_len(length - 1);
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return length;
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acpigen_pop_len();
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}
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static int generate_C_state_entries(void)
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static void generate_C_state_entries(void)
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{
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struct cpu_info *info;
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struct cpu_driver *cpu;
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int len, lenif;
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struct device *lapic;
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struct cpu_intel_model_2065x_config *conf = NULL;
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/* Find the SpeedStep CPU in the device tree using magic APIC ID */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic)
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return 0;
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return;
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conf = lapic->chip_info;
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if (!conf)
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return 0;
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return;
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/* Find CPU map of supported C-states */
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info = cpu_info();
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if (!info)
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return 0;
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return;
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cpu = find_cpu_driver(info->cpu);
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if (!cpu || !cpu->cstates)
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return 0;
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return;
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len = acpigen_emit_byte(0x14); /* MethodOp */
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len += acpigen_write_len_f(); /* PkgLength */
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len += acpigen_emit_namestring("_CST");
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len += acpigen_emit_byte(0x00); /* No Arguments */
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acpigen_emit_byte(0x14); /* MethodOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("_CST");
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acpigen_emit_byte(0x00); /* No Arguments */
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/* If running on AC power */
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len += acpigen_emit_byte(0xa0); /* IfOp */
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lenif = acpigen_write_len_f(); /* PkgLength */
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lenif += acpigen_emit_namestring("PWRS");
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lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
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lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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acpigen_emit_byte(0xa0); /* IfOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("PWRS");
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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conf->c2_acpower, conf->c3_acpower);
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acpigen_patch_len(lenif - 1);
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len += lenif;
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acpigen_pop_len();
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/* Else on battery power */
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len += acpigen_emit_byte(0xa4); /* ReturnOp */
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len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_battery,
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conf->c2_battery, conf->c3_battery);
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acpigen_patch_len(len - 1);
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return len;
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acpigen_pop_len();
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}
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static acpi_tstate_t tss_table_fine[] = {
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@ -208,9 +204,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static int generate_P_state_entries(int core, int cores_per_package)
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static void generate_P_state_entries(int core, int cores_per_package)
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{
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int len, len_pss;
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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int coord_type, power_max, num_entries;
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int ratio, power, clock, clock_max;
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@ -242,16 +237,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
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power_max = 25000;
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/* Write _PCT indicating use of FFixedHW */
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len = acpigen_write_empty_PCT();
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acpigen_write_empty_PCT();
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/* Write _PPC with no limit on supported P-state */
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len += acpigen_write_PPC_NVS();
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acpigen_write_PPC_NVS();
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/* Write PSD indicating configured coordination type */
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len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
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acpigen_write_PSD_package(core, cores_per_package, coord_type);
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/* Add P-state entries in _PSS table */
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len += acpigen_write_name("_PSS");
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acpigen_write_name("_PSS");
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/* Determine ratio points */
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ratio_step = PSS_RATIO_STEP;
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@ -264,13 +259,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
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/* P[T] is Turbo state if enabled */
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if (get_turbo_state() == TURBO_ENABLED) {
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/* _PSS package count including Turbo */
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len_pss = acpigen_write_package(num_entries + 2);
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acpigen_write_package(num_entries + 2);
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msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
|
||||
ratio_turbo = msr.lo & 0xff;
|
||||
|
||||
/* Add entry for Turbo ratio */
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock_max + 1, /*MHz*/
|
||||
power_max, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -279,11 +274,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
ratio_turbo); /*status*/
|
||||
} else {
|
||||
/* _PSS package count without Turbo */
|
||||
len_pss = acpigen_write_package(num_entries + 1);
|
||||
acpigen_write_package(num_entries + 1);
|
||||
}
|
||||
|
||||
/* First regular entry is max non-turbo ratio */
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock_max, /*MHz*/
|
||||
power_max, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -299,7 +294,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
power = calculate_power(power_max, ratio_max, ratio);
|
||||
clock = ratio * NEHALEM_BCLK + ratio / 3;
|
||||
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock, /*MHz*/
|
||||
power, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -309,15 +304,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
}
|
||||
|
||||
/* Fix package length */
|
||||
len_pss--;
|
||||
acpigen_patch_len(len_pss);
|
||||
|
||||
return len + len_pss;
|
||||
acpigen_pop_len();
|
||||
}
|
||||
|
||||
void generate_cpu_entries(void)
|
||||
{
|
||||
int len_pr;
|
||||
int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
|
||||
int totalcores = dev_count_cpu();
|
||||
int cores_per_package = get_cores_per_package();
|
||||
|
|
@ -334,23 +325,22 @@ void generate_cpu_entries(void)
|
|||
}
|
||||
|
||||
/* Generate processor \_PR.CPUx */
|
||||
len_pr = acpigen_write_processor(
|
||||
acpigen_write_processor(
|
||||
(cpuID-1)*cores_per_package+coreID-1,
|
||||
pcontrol_blk, plen);
|
||||
|
||||
/* Generate P-state tables */
|
||||
len_pr += generate_P_state_entries(
|
||||
generate_P_state_entries(
|
||||
cpuID-1, cores_per_package);
|
||||
|
||||
/* Generate C-state tables */
|
||||
len_pr += generate_C_state_entries();
|
||||
generate_C_state_entries();
|
||||
|
||||
/* Generate T-state tables */
|
||||
len_pr += generate_T_state_entries(
|
||||
generate_T_state_entries(
|
||||
cpuID-1, cores_per_package);
|
||||
|
||||
len_pr--;
|
||||
acpigen_patch_len(len_pr);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -48,10 +48,10 @@ static int get_cores_per_package(void)
|
|||
return cores;
|
||||
}
|
||||
|
||||
static int generate_cstate_entries(acpi_cstate_t *cstates,
|
||||
static void generate_cstate_entries(acpi_cstate_t *cstates,
|
||||
int c1, int c2, int c3)
|
||||
{
|
||||
int length, cstate_count = 0;
|
||||
int cstate_count = 0;
|
||||
|
||||
/* Count number of active C-states */
|
||||
if (c1 > 0)
|
||||
|
|
@ -61,74 +61,70 @@ static int generate_cstate_entries(acpi_cstate_t *cstates,
|
|||
if (c3 > 0)
|
||||
++cstate_count;
|
||||
if (!cstate_count)
|
||||
return 0;
|
||||
return;
|
||||
|
||||
length = acpigen_write_package(cstate_count + 1);
|
||||
length += acpigen_write_byte(cstate_count);
|
||||
acpigen_write_package(cstate_count + 1);
|
||||
acpigen_write_byte(cstate_count);
|
||||
|
||||
/* Add an entry if the level is enabled */
|
||||
if (c1 > 0) {
|
||||
cstates[c1].ctype = 1;
|
||||
length += acpigen_write_CST_package_entry(&cstates[c1]);
|
||||
acpigen_write_CST_package_entry(&cstates[c1]);
|
||||
}
|
||||
if (c2 > 0) {
|
||||
cstates[c2].ctype = 2;
|
||||
length += acpigen_write_CST_package_entry(&cstates[c2]);
|
||||
acpigen_write_CST_package_entry(&cstates[c2]);
|
||||
}
|
||||
if (c3 > 0) {
|
||||
cstates[c3].ctype = 3;
|
||||
length += acpigen_write_CST_package_entry(&cstates[c3]);
|
||||
acpigen_write_CST_package_entry(&cstates[c3]);
|
||||
}
|
||||
|
||||
acpigen_patch_len(length - 1);
|
||||
return length;
|
||||
acpigen_pop_len();
|
||||
}
|
||||
|
||||
static int generate_C_state_entries(void)
|
||||
static void generate_C_state_entries(void)
|
||||
{
|
||||
struct cpu_info *info;
|
||||
struct cpu_driver *cpu;
|
||||
int len, lenif;
|
||||
struct device *lapic;
|
||||
struct cpu_intel_model_206ax_config *conf = NULL;
|
||||
|
||||
/* Find the SpeedStep CPU in the device tree using magic APIC ID */
|
||||
lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
|
||||
if (!lapic)
|
||||
return 0;
|
||||
return;
|
||||
conf = lapic->chip_info;
|
||||
if (!conf)
|
||||
return 0;
|
||||
return;
|
||||
|
||||
/* Find CPU map of supported C-states */
|
||||
info = cpu_info();
|
||||
if (!info)
|
||||
return 0;
|
||||
return;
|
||||
cpu = find_cpu_driver(info->cpu);
|
||||
if (!cpu || !cpu->cstates)
|
||||
return 0;
|
||||
return;
|
||||
|
||||
len = acpigen_emit_byte(0x14); /* MethodOp */
|
||||
len += acpigen_write_len_f(); /* PkgLength */
|
||||
len += acpigen_emit_namestring("_CST");
|
||||
len += acpigen_emit_byte(0x00); /* No Arguments */
|
||||
acpigen_emit_byte(0x14); /* MethodOp */
|
||||
acpigen_write_len_f(); /* PkgLength */
|
||||
acpigen_emit_namestring("_CST");
|
||||
acpigen_emit_byte(0x00); /* No Arguments */
|
||||
|
||||
/* If running on AC power */
|
||||
len += acpigen_emit_byte(0xa0); /* IfOp */
|
||||
lenif = acpigen_write_len_f(); /* PkgLength */
|
||||
lenif += acpigen_emit_namestring("PWRS");
|
||||
lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
|
||||
lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
|
||||
acpigen_emit_byte(0xa0); /* IfOp */
|
||||
acpigen_write_len_f(); /* PkgLength */
|
||||
acpigen_emit_namestring("PWRS");
|
||||
acpigen_emit_byte(0xa4); /* ReturnOp */
|
||||
generate_cstate_entries(cpu->cstates, conf->c1_acpower,
|
||||
conf->c2_acpower, conf->c3_acpower);
|
||||
acpigen_patch_len(lenif - 1);
|
||||
len += lenif;
|
||||
acpigen_pop_len();
|
||||
|
||||
/* Else on battery power */
|
||||
len += acpigen_emit_byte(0xa4); /* ReturnOp */
|
||||
len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
|
||||
acpigen_emit_byte(0xa4); /* ReturnOp */
|
||||
generate_cstate_entries(cpu->cstates, conf->c1_battery,
|
||||
conf->c2_battery, conf->c3_battery);
|
||||
acpigen_patch_len(len - 1);
|
||||
return len;
|
||||
acpigen_pop_len();
|
||||
}
|
||||
|
||||
static acpi_tstate_t tss_table_fine[] = {
|
||||
|
|
@ -208,9 +204,8 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
|
|||
return (int)power;
|
||||
}
|
||||
|
||||
static int generate_P_state_entries(int core, int cores_per_package)
|
||||
static void generate_P_state_entries(int core, int cores_per_package)
|
||||
{
|
||||
int len, len_pss;
|
||||
int ratio_min, ratio_max, ratio_turbo, ratio_step;
|
||||
int coord_type, power_max, power_unit, num_entries;
|
||||
int ratio, power, clock, clock_max;
|
||||
|
|
@ -245,16 +240,16 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
|
||||
|
||||
/* Write _PCT indicating use of FFixedHW */
|
||||
len = acpigen_write_empty_PCT();
|
||||
acpigen_write_empty_PCT();
|
||||
|
||||
/* Write _PPC with no limit on supported P-state */
|
||||
len += acpigen_write_PPC_NVS();
|
||||
acpigen_write_PPC_NVS();
|
||||
|
||||
/* Write PSD indicating configured coordination type */
|
||||
len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
|
||||
acpigen_write_PSD_package(core, cores_per_package, coord_type);
|
||||
|
||||
/* Add P-state entries in _PSS table */
|
||||
len += acpigen_write_name("_PSS");
|
||||
acpigen_write_name("_PSS");
|
||||
|
||||
/* Determine ratio points */
|
||||
ratio_step = PSS_RATIO_STEP;
|
||||
|
|
@ -267,13 +262,13 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
/* P[T] is Turbo state if enabled */
|
||||
if (get_turbo_state() == TURBO_ENABLED) {
|
||||
/* _PSS package count including Turbo */
|
||||
len_pss = acpigen_write_package(num_entries + 2);
|
||||
acpigen_write_package(num_entries + 2);
|
||||
|
||||
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
|
||||
ratio_turbo = msr.lo & 0xff;
|
||||
|
||||
/* Add entry for Turbo ratio */
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock_max + 1, /*MHz*/
|
||||
power_max, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -282,11 +277,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
ratio_turbo << 8); /*status*/
|
||||
} else {
|
||||
/* _PSS package count without Turbo */
|
||||
len_pss = acpigen_write_package(num_entries + 1);
|
||||
acpigen_write_package(num_entries + 1);
|
||||
}
|
||||
|
||||
/* First regular entry is max non-turbo ratio */
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock_max, /*MHz*/
|
||||
power_max, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -302,7 +297,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
power = calculate_power(power_max, ratio_max, ratio);
|
||||
clock = ratio * SANDYBRIDGE_BCLK;
|
||||
|
||||
len_pss += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
clock, /*MHz*/
|
||||
power, /*mW*/
|
||||
PSS_LATENCY_TRANSITION, /*lat1*/
|
||||
|
|
@ -312,15 +307,11 @@ static int generate_P_state_entries(int core, int cores_per_package)
|
|||
}
|
||||
|
||||
/* Fix package length */
|
||||
len_pss--;
|
||||
acpigen_patch_len(len_pss);
|
||||
|
||||
return len + len_pss;
|
||||
acpigen_pop_len();
|
||||
}
|
||||
|
||||
void generate_cpu_entries(void)
|
||||
{
|
||||
int len_pr;
|
||||
int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
|
||||
int totalcores = dev_count_cpu();
|
||||
int cores_per_package = get_cores_per_package();
|
||||
|
|
@ -337,23 +328,22 @@ void generate_cpu_entries(void)
|
|||
}
|
||||
|
||||
/* Generate processor \_PR.CPUx */
|
||||
len_pr = acpigen_write_processor(
|
||||
acpigen_write_processor(
|
||||
(cpuID-1)*cores_per_package+coreID-1,
|
||||
pcontrol_blk, plen);
|
||||
|
||||
/* Generate P-state tables */
|
||||
len_pr += generate_P_state_entries(
|
||||
generate_P_state_entries(
|
||||
cpuID-1, cores_per_package);
|
||||
|
||||
/* Generate C-state tables */
|
||||
len_pr += generate_C_state_entries();
|
||||
generate_C_state_entries();
|
||||
|
||||
/* Generate T-state tables */
|
||||
len_pr += generate_T_state_entries(
|
||||
generate_T_state_entries(
|
||||
cpuID-1, cores_per_package);
|
||||
|
||||
len_pr--;
|
||||
acpigen_patch_len(len_pr);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,18 +82,17 @@ static int get_fsb(void)
|
|||
return 600;
|
||||
}
|
||||
|
||||
static int gen_pstate_entries(const sst_table_t *const pstates,
|
||||
static void gen_pstate_entries(const sst_table_t *const pstates,
|
||||
const int cpuID, const int cores_per_package,
|
||||
const uint8_t coordination)
|
||||
{
|
||||
int i;
|
||||
int len, len_ps;
|
||||
int frequency;
|
||||
|
||||
len = acpigen_write_empty_PCT();
|
||||
len += acpigen_write_PSD_package(
|
||||
acpigen_write_empty_PCT();
|
||||
acpigen_write_PSD_package(
|
||||
cpuID, cores_per_package, coordination);
|
||||
len += acpigen_write_name("_PSS");
|
||||
acpigen_write_name("_PSS");
|
||||
|
||||
const int fsb3 = get_fsb();
|
||||
const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(
|
||||
|
|
@ -107,7 +106,7 @@ static int gen_pstate_entries(const sst_table_t *const pstates,
|
|||
printk(BIOS_DEBUG, "adding %x P-States between "
|
||||
"busratio %x and %x, ""incl. P0\n",
|
||||
pstates->num_states, min_ratio2 / 2, max_ratio2 / 2);
|
||||
len_ps = acpigen_write_package(pstates->num_states);
|
||||
acpigen_write_package(pstates->num_states);
|
||||
for (i = 0; i < pstates->num_states; ++i) {
|
||||
const sst_state_t *const pstate = &pstates->states[i];
|
||||
/* Report frequency of turbo mode as that of HFM + 1. */
|
||||
|
|
@ -119,19 +118,14 @@ static int gen_pstate_entries(const sst_table_t *const pstates,
|
|||
frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12;
|
||||
else
|
||||
frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6;
|
||||
len_ps += acpigen_write_PSS_package(
|
||||
acpigen_write_PSS_package(
|
||||
frequency, pstate->power, 0, 0,
|
||||
SPEEDSTEP_ENCODE_STATE(*pstate),
|
||||
SPEEDSTEP_ENCODE_STATE(*pstate));
|
||||
}
|
||||
len_ps--;
|
||||
acpigen_patch_len(len_ps);
|
||||
acpigen_pop_len();
|
||||
|
||||
len += acpigen_write_PPC(0);
|
||||
|
||||
len += len_ps;
|
||||
|
||||
return len;
|
||||
acpigen_write_PPC(0);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -139,7 +133,6 @@ static int gen_pstate_entries(const sst_table_t *const pstates,
|
|||
*/
|
||||
void generate_cpu_entries(void)
|
||||
{
|
||||
int len_pr;
|
||||
int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
|
||||
int totalcores = determine_total_number_of_cores();
|
||||
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
|
||||
|
|
@ -171,21 +164,20 @@ void generate_cpu_entries(void)
|
|||
}
|
||||
|
||||
/* Generate processor \_PR.CPUx. */
|
||||
len_pr = acpigen_write_processor(
|
||||
acpigen_write_processor(
|
||||
cpuID * cores_per_package + coreID - 1,
|
||||
pcontrol_blk, plen);
|
||||
|
||||
/* Generate p-state entries. */
|
||||
len_pr += gen_pstate_entries(&pstates, cpuID,
|
||||
gen_pstate_entries(&pstates, cpuID,
|
||||
cores_per_package, coordination);
|
||||
|
||||
/* Generate c-state entries. */
|
||||
if (num_cstates > 0)
|
||||
len_pr += acpigen_write_CST_package(
|
||||
acpigen_write_CST_package(
|
||||
cstates, num_cstates);
|
||||
|
||||
len_pr--;
|
||||
acpigen_patch_len(len_pr);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -682,8 +682,6 @@ static void southbridge_inject_dsdt(void)
|
|||
opregion = igd_make_opregion();
|
||||
|
||||
if (gnvs) {
|
||||
int scopelen;
|
||||
|
||||
memset(gnvs, 0, sizeof (*gnvs));
|
||||
|
||||
acpi_create_gnvs(gnvs);
|
||||
|
|
@ -702,9 +700,9 @@ static void southbridge_inject_dsdt(void)
|
|||
smm_setup_structures(gnvs, NULL, NULL);
|
||||
|
||||
/* Add it to DSDT. */
|
||||
scopelen = acpigen_write_scope("\\");
|
||||
scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_patch_len(scopelen - 1);
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -640,8 +640,6 @@ static void southbridge_inject_dsdt(void)
|
|||
opregion = igd_make_opregion();
|
||||
|
||||
if (gnvs) {
|
||||
int scopelen;
|
||||
|
||||
memset(gnvs, 0, sizeof (*gnvs));
|
||||
|
||||
acpi_create_gnvs(gnvs);
|
||||
|
|
@ -651,9 +649,9 @@ static void southbridge_inject_dsdt(void)
|
|||
smm_setup_structures(gnvs, NULL, NULL);
|
||||
|
||||
/* Add it to DSDT. */
|
||||
scopelen = acpigen_write_scope("\\");
|
||||
scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_patch_len(scopelen - 1);
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -675,8 +675,6 @@ static void southbridge_inject_dsdt(void)
|
|||
opregion = igd_make_opregion();
|
||||
|
||||
if (gnvs) {
|
||||
int scopelen;
|
||||
|
||||
memset(gnvs, 0, sizeof (*gnvs));
|
||||
|
||||
acpi_create_gnvs(gnvs);
|
||||
|
|
@ -686,9 +684,9 @@ static void southbridge_inject_dsdt(void)
|
|||
smm_setup_structures(gnvs, NULL, NULL);
|
||||
|
||||
/* Add it to SSDT. */
|
||||
scopelen = acpigen_write_scope("\\");
|
||||
scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_patch_len(scopelen - 1);
|
||||
acpigen_write_scope("\\");
|
||||
acpigen_write_name_dword("NVSA", (u32) gnvs);
|
||||
acpigen_pop_len();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue