From 227c64952218c7ac02548f15bb9fe1bae9ed9e02 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 22 Mar 2021 14:44:58 +0100 Subject: [PATCH] soc/amd/cezanne: select HAVE_EM100_SUPPORT This makes the EM100 option visible in Kconfig that makes sure that the SPI settings that coreboot applies are valid for the EM100 that has some limitations on the maximum SPI frequency and possibly on the supported SPI modes. For the PSP SPI settings, the mainboard still might need to provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly integrated for Cezanne. Signed-off-by: Felix Held Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Raul Rangel --- src/soc/amd/cezanne/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7a69cc7f5e..5e0e1a6d6d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -22,6 +22,7 @@ config SOC_SPECIFIC_OPTIONS select FSP_COMPRESS_FSP_S_LZMA select HAVE_ACPI_TABLES select HAVE_CF9_RESET + select HAVE_EM100_SUPPORT select HAVE_FSP_GOP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE