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mb/google/volteer: Only enable TBT root ports if USB4 is supported 

TBT ports should be disabled if the DB is a USB3 DB. It is assumed if
the DB doesn't support USB4 the platform as a whole should only be USB3
capable and TBT functionality on both ports should not be enabled.

BUG=NONE
BRANCH=NONE
TEST=Built coreboot and verified that TBT was disabled on platform with
USB3 DB and enabled on platform with USB4/TBT DB

Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Brandon Breitenstein 2020-07-23 14:40:14 -07:00 committed by Duncan Laurie
parent 041fcf5902
commit 228d0e5078
1 changed files with 12 additions and 3 deletions
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15
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -381,8 +381,14 @@ chip soc/intel/tigerlake
end # DPTF 0x9A03
device pci 05.0 off end # IPU 0x9A19
device pci 06.0 off end # PEG60 0x9A09
device pci 07.0 on end # TBT_PCIe0 0x9A23
device pci 07.1 on end # TBT_PCIe1 0x9A25
device pci 07.0 on # TBT_PCIe0 0x9A23
probe DB_USB USB4_GEN2
probe DB_USB USB4_GEN3
end
device pci 07.1 on # TBT_PCIe1 0x9A25
probe DB_USB USB4_GEN2
probe DB_USB USB4_GEN3
end
device pci 07.2 off end # TBT_PCIe2 0x9A27
device pci 07.3 off end # TBT_PCIe3 0x9A29
device pci 08.0 on end # GNA 0x9A11
@ -390,7 +396,10 @@ chip soc/intel/tigerlake
device pci 0a.0 off end # Crash-log SRAM 0x9A0D
device pci 0d.0 on end # USB xHCI 0x9A13
device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
device pci 0d.2 on end # TBT DMA0 0x9A1B
device pci 0d.2 on # TBT DMA0 0x9A1B
probe DB_USB USB4_GEN2
probe DB_USB USB4_GEN3
end
device pci 0d.3 off end # TBT DMA1 0x9A1D
device pci 0e.0 off end # VMD 0x9A0B