tegra: Clean up USB code
Pull out the common usb setup utmip functions from t124 into tegra usb.h. These can be reused for t132 as well. BUG=chrome-os-partner:31293 BRANCH=None TEST=Compiles successfully for nyan, big and blaze Change-Id: Idddd40e409b56875436db6918d05f2889d83870b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 12f12cb30a033cce645f53457d13a987aeec22a1 Original-Change-Id: I83f83bafad0f52ad651fe5989430f41142803f2b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211200 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8927 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
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2296774af6
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@ -29,7 +29,7 @@
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#include <soc/nvidia/tegra124/mc.h>
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#include <soc/nvidia/tegra124/pmc.h>
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#include <soc/nvidia/tegra124/spi.h>
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#include <soc/nvidia/tegra124/usb.h>
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#include <soc/nvidia/tegra/usb.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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@ -232,9 +232,9 @@ static void mainboard_init(device_t dev)
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CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
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CLK_X_AFC5);
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usb_setup_utmip1();
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usb_setup_utmip((void*)TEGRA_USBD_BASE);
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/* USB2 is the camera, we don't need it in firmware */
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usb_setup_utmip3();
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usb_setup_utmip((void*)TEGRA_USB3_BASE);
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setup_pinmux();
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@ -29,7 +29,7 @@
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#include <soc/nvidia/tegra124/mc.h>
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#include <soc/nvidia/tegra124/pmc.h>
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#include <soc/nvidia/tegra124/spi.h>
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#include <soc/nvidia/tegra124/usb.h>
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#include <soc/nvidia/tegra/usb.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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@ -230,9 +230,9 @@ static void mainboard_init(device_t dev)
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CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
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CLK_X_AFC5);
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usb_setup_utmip1();
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usb_setup_utmip((void*)TEGRA_USBD_BASE);
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/* USB2 is the camera, we don't need it in firmware */
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usb_setup_utmip3();
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usb_setup_utmip((void*)TEGRA_USB3_BASE);
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setup_pinmux();
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@ -29,7 +29,7 @@
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#include <soc/nvidia/tegra124/mc.h>
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#include <soc/nvidia/tegra124/pmc.h>
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#include <soc/nvidia/tegra124/spi.h>
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#include <soc/nvidia/tegra124/usb.h>
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#include <soc/nvidia/tegra/usb.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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@ -230,9 +230,9 @@ static void mainboard_init(device_t dev)
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CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
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CLK_X_AFC5);
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usb_setup_utmip1();
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usb_setup_utmip2();
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usb_setup_utmip3();
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usb_setup_utmip((void*)TEGRA_USBD_BASE);
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usb_setup_utmip((void*)TEGRA_USB2_BASE);
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usb_setup_utmip((void*)TEGRA_USB3_BASE);
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setup_pinmux();
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@ -24,9 +24,131 @@
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#include "usb.h"
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/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
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void usb_setup_utmip(struct usb_ctlr *usb)
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struct utmip_ctlr {
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u32 pll0;
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u32 pll1;
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u32 xcvr0;
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u32 bias0;
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u32 hsrx0;
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u32 hsrx1;
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u32 fslsrx0;
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u32 fslsrx1;
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u32 tx;
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u32 misc0;
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u32 misc1;
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u32 debounce;
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u32 batchrgr;
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u32 spare;
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u32 xcvr1;
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u32 bias1;
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u32 bias_sts;
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u32 chrgr_debounce;
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u32 misc_sts;
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u32 pmc_wakeup;
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};
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check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800);
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struct usb_ctlr {
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u32 id;
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u32 _rsv0;
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u32 host;
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u32 device;
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u32 txbuf; /* 0x010 */
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u32 rxbuf;
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u32 _rsv1[58];
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u16 ehci_caplen; /* 0x100 */
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u16 ehci_version;
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u32 ehci_hcsp;
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u32 ehci_hccp;
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u32 _rsv2[5];
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u32 dci_version; /* 0x120 */
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u32 dcc_params;
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u32 extsts;
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u32 extintr;
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u32 ehci_usbcmd; /* 0x130 */
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u32 ehci_usbsts;
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u32 ehci_usbintr;
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u32 ehci_frindex;
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u32 _rsv3; /* 0x140 */
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u32 ehci_periodic_base;
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u32 ehci_async_base;
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u32 async_ttsts;
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u32 burst_size; /* 0x150 */
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u32 tx_fill_tuning;
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u32 _rsv4;
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u32 icusb_ctrl;
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u32 ulpi_viewport; /* 0x160 */
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u32 _rsv5[4];
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u32 ehci_portsc;
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u32 _rsv6[15];
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u32 lpm_ctrl;
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u32 _rsv7[15];
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u32 otgsc;
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u32 usb_mode;
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u32 _rsv8;
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u32 ep_nak; /* 0x200 */
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u32 ep_nak_enable;
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u32 ep_setup;
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u32 ep_init;
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u32 ep_deinit;
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u32 ep_sts;
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u32 ep_complete;
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u32 ep_ctrl[16];
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u32 _rsv9[105];
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u32 suspend_ctrl; /* 0x400 */
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u32 vbus_sensors;
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u32 vbus_wakeup_id;
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u32 alt_vbus_sts;
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u32 legacy_ctrl;
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u32 _rsv10[3];
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u32 interpacket_delay;
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u32 _rsv11[27];
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u32 resume_delay;
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u32 _rsv12;
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u32 spare;
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u32 _rsv13[9];
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u32 new_ctrl;
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u32 _rsv14[207];
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struct utmip_ctlr utmip; /* 0x800 */
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};
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check_member(usb_ctlr, utmip, 0x800);
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/*
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* Tegra EHCI controllers need their usb_mode, lpm_ctrl and tx_fill_tuning
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* registers initialized after every EHCI reset and before any other actions
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* (such as Run/Stop bit) are taken. We reset the controller here, set those
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* registers and rely on the fact that libpayload doesn't reset EHCI controllers
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* on initialization for whatever weird reason. This is ugly, fragile, and I
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* really don't like it, but making this work will require an ugly hack one way
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* or another so we might as well take the path of least resistance for now.
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*/
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static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
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{
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int timeout = 1000;
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write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
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/* TODO: Resets are long, find way to parallelize... or just use XHCI */
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while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
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/* wait for HC to reset */;
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if (!timeout) {
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printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb);
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return;
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}
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/* Controller mode: HOST */
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write32(3 << 0, &usb->usb_mode);
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/* Parallel transceiver selct */
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write32(type << 29, &usb->lpm_ctrl);
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/* Tx FIFO Burst thresh */
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write32(0x10 << 16, &usb->tx_fill_tuning);
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}
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/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
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void usb_setup_utmip(void *usb_base)
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{
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struct usb_ctlr *usb = (struct usb_ctlr *)usb_base;
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/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
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int khz = clock_get_pll_input_khz();
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@ -90,32 +212,8 @@ void usb_setup_utmip(struct usb_ctlr *usb)
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write32(1 << 12 | /* UTMI+ enable */
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0 << 11 | /* UTMI+ reset */
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0, &usb->suspend_ctrl);
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usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
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printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);
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}
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/*
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* Tegra EHCI controllers need their usb_mode, lpm_ctrl and tx_fill_tuning
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* registers initialized after every EHCI reset and before any other actions
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* (such as Run/Stop bit) are taken. We reset the controller here, set those
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* registers and rely on the fact that libpayload doesn't reset EHCI controllers
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* on initialization for whatever weird reason. This is ugly, fragile, and I
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* really don't like it, but making this work will require an ugly hack one way
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* or another so we might as well take the path of least resistance for now.
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*/
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void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
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{
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int timeout = 1000;
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write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
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/* TODO: Resets are long, find way to parallelize... or just use XHCI */
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while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
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/* wait for HC to reset */;
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if (!timeout) {
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printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb);
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return;
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}
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write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */
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write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */
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write32(0x10 << 16, &usb->tx_fill_tuning); /* Tx FIFO Burst thresh */
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}
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@ -22,95 +22,6 @@
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#include <stdint.h>
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struct utmip_ctlr {
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u32 pll0;
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u32 pll1;
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u32 xcvr0;
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u32 bias0;
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u32 hsrx0;
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u32 hsrx1;
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u32 fslsrx0;
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u32 fslsrx1;
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u32 tx;
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u32 misc0;
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u32 misc1;
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u32 debounce;
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u32 batchrgr;
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u32 spare;
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u32 xcvr1;
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u32 bias1;
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u32 bias_sts;
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u32 chrgr_debounce;
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u32 misc_sts;
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u32 pmc_wakeup;
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};
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check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800);
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struct usb_ctlr {
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u32 id;
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u32 _rsv0;
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u32 host;
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u32 device;
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u32 txbuf; /* 0x010 */
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u32 rxbuf;
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u32 _rsv1[58];
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u16 ehci_caplen; /* 0x100 */
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u16 ehci_version;
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u32 ehci_hcsp;
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u32 ehci_hccp;
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u32 _rsv2[5];
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u32 dci_version; /* 0x120 */
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u32 dcc_params;
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u32 extsts;
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u32 extintr;
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u32 ehci_usbcmd; /* 0x130 */
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u32 ehci_usbsts;
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u32 ehci_usbintr;
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u32 ehci_frindex;
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u32 _rsv3; /* 0x140 */
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u32 ehci_periodic_base;
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u32 ehci_async_base;
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u32 async_ttsts;
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u32 burst_size; /* 0x150 */
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u32 tx_fill_tuning;
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u32 _rsv4;
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u32 icusb_ctrl;
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u32 ulpi_viewport; /* 0x160 */
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u32 _rsv5[4];
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u32 ehci_portsc;
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u32 _rsv6[15];
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u32 lpm_ctrl;
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u32 _rsv7[15];
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u32 otgsc;
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u32 usb_mode;
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u32 _rsv8;
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u32 ep_nak; /* 0x200 */
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u32 ep_nak_enable;
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u32 ep_setup;
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u32 ep_init;
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u32 ep_deinit;
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u32 ep_sts;
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u32 ep_complete;
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u32 ep_ctrl[16];
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u32 _rsv9[105];
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u32 suspend_ctrl; /* 0x400 */
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u32 vbus_sensors;
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u32 vbus_wakeup_id;
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u32 alt_vbus_sts;
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u32 legacy_ctrl;
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u32 _rsv10[3];
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u32 interpacket_delay;
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u32 _rsv11[27];
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u32 resume_delay;
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u32 _rsv12;
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u32 spare;
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u32 _rsv13[9];
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u32 new_ctrl;
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u32 _rsv14[207];
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struct utmip_ctlr utmip; /* 0x800 */
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};
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check_member(usb_ctlr, utmip, 0x800);
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enum usb_phy_type { /* For use in lpm_ctrl[31:29] */
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USB_PHY_UTMIP = 0,
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USB_PHY_ULPI = 2,
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USB_PHY_HSIC = 4,
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};
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void usb_setup_utmip(struct usb_ctlr *usb);
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void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type);
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void usb_setup_utmip(void *usb_base);
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#endif
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@ -1,50 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013, Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __SOC_NVIDIA_TEGRA124_USB_H_
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#define __SOC_NVIDIA_TEGRA124_USB_H_
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/nvidia/tegra/usb.h>
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static inline void usb_setup_utmip1(void)
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{
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struct usb_ctlr *usb = (void *)TEGRA_USBD_BASE;
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usb_setup_utmip(usb);
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usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
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printk(BIOS_DEBUG, "USBD controller set up with UTMI+ PHY\n");
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}
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static inline void usb_setup_utmip2(void)
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{
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struct usb_ctlr *usb = (void *)TEGRA_USB2_BASE;
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usb_setup_utmip(usb);
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usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
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printk(BIOS_DEBUG, "USB2 controller set up with UTMI+ PHY\n");
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}
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static inline void usb_setup_utmip3(void)
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{
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struct usb_ctlr *usb = (void *)TEGRA_USB3_BASE;
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usb_setup_utmip(usb);
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usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
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printk(BIOS_DEBUG, "USB3 controller set up with UTMI+ PHY\n");
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}
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#endif /* __SOC_NVIDIA_TEGRA124_USB_H_ */
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