mb/google/cherry: Fix incorrect timestamps in eventlog

The eventlog requires RTC to provide correct timestamps, so we have to
turn on the config and add the common drivers.

BUG=b:199003609
TEST=check timestamp in 'mosys eventlog list'
BRANCH=none

Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Change-Id: Ia382cd023fcbfdf2c1efeb7b32c0b99feb71effa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Chen-Tsung Hsieh 2021-09-06 12:58:39 +08:00 committed by Felix Held
parent f88b90f6a9
commit 229e6bc95f
2 changed files with 3 additions and 0 deletions

View File

@ -12,6 +12,7 @@ config VBOOT
config BOARD_SPECIFIC_OPTIONS
def_bool y
select RTC
select SOC_MEDIATEK_MT8195
select BOARD_ROMSIZE_KB_8192
select MAINBOARD_HAS_CHROMEOS

View File

@ -67,6 +67,8 @@ ramstage-y += mt6360.c
ramstage-y += ../common/mtcmos.c mtcmos.c
ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c
ramstage-y += ../common/pll.c pll.c
ramstage-y += ../common/pmif.c
ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += soc.c
ramstage-y += ../common/sspm.c