mb/google/guybrush: Set up FW_CONFIG fields

BUG=b:180523962
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/google/guybrush/Kconfig

@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select AMD_SOC_CONSOLE_UART
 	select BOARD_ROMSIZE_KB_16384
+	select FW_CONFIG
 	select MAINBOARD_HAS_CHROMEOS
 	select SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI

src/mainboard/google/guybrush/variants/guybrush/overridetree.cb

@@ -1,4 +1,36 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
+fw_config
+	field USB_DB 0 1
+		option USB_DB_A1_PS8811_C1_PS8818 0
+		option USB_DB_A1_ANX7491_C1_ANX7451 1
+	end
+	field FORM_FACTOR 2
+		option FORM_FACTOR_CLAMSHELL 0
+		option FORM_FACTOR_CONVERTIBLE 1
+	end
+	field KB_BL 3
+		option KB_BL_ABSENT 0
+		option KB_BL_PRESENT 1
+	end
+	field FP 4
+		option FP_ABSENT 0
+		option FP_PRESENT 1
+	end
+	field WLAN 5 6
+		option WLAN_WCN6856 0
+		option WLAN_RTL8852 1
+	end
+	field WWAN 7 8
+		option WWAN_DIASABLED 0
+		option WWAN_L850GL 1
+		option WWAN_FM350GL 2
+	end
+	field BEEP_MODE 9
+		option BEEP_MODE_AMP 0
+		option BEEP_MODE_BIT_BANG 1
+	end
+end
+
 chip soc/amd/cezanne
 	device domain 0 on
 	end # domain