soc/intel/cannonlake: Tell FSPM UART port number

Cannonlake FSP will send debug message on selected UART port, use same
coreboot UART debug port to FSP.

TEST=Boot up with board have UART port 0 and can see the print of FSP

Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/romstage/romstage.c

@@ -92,6 +92,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 	m_cfg->EnableC6Dram = config->enable_c6dram;
 	/* Disable Cpu Ratio Override temporary. */
 	m_cfg->CpuRatio = 0;
+	m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)