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soc/intel/cannonlake: Tell FSPM UART port number 

Cannonlake FSP will send debug message on selected UART port, use same
coreboot UART debug port to FSP.

TEST=Boot up with board have UART port 0 and can see the print of FSP

Change-Id: Id72e459d2fbb1f16b005d22fac66667086880384
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-11-30 10:10:59 -08:00 committed by Martin Roth
parent 1731a33e32
commit 22d20d6f14
1 changed files with 1 additions and 0 deletions
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src/soc/intel/cannonlake/romstage/romstage.c
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@ -92,6 +92,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->EnableC6Dram = config->enable_c6dram; m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable Cpu Ratio Override temporary. */ /* Disable Cpu Ratio Override temporary. */
m_cfg->CpuRatio = 0; m_cfg->CpuRatio = 0;
m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)