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southbridge/amd/sb700: Disable broken SATA MSI functionality

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Change-Id: I4e0a52eb90910604f8640ad7533b5d71be6c8e20
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11983
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Timothy Pearson 2015-06-09 19:12:35 -05:00 committed by Stefan Reinauer
parent f89a05ed9f
commit 22dfccf5b7
1 changed files with 4 additions and 3 deletions
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7
src/southbridge/amd/sb700/early_setup.c
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@ -658,6 +658,7 @@ static void sb700_pci_cfg(void)
{ {
device_t dev; device_t dev;
u8 byte; u8 byte;
uint8_t acpi_s1_supported = 1;
/* SMBus Device, BDF:0-20-0 */ /* SMBus Device, BDF:0-20-0 */
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
@ -710,10 +711,10 @@ static void sb700_pci_cfg(void)
byte = pci_read_config8(dev, 0x40); byte = pci_read_config8(dev, 0x40);
byte |= 1 << 0; byte |= 1 << 0;
pci_write_config8(dev, 0x40, byte); pci_write_config8(dev, 0x40, byte);
if (get_sb700_revision(pci_locate_device(PCI_ID(0x1002, 0x4385), 0)) <= 0x12) if (acpi_s1_supported)
pci_write_config8(dev, 0x34, 0x70); /* set 0x61 to 0x70 if S1 is not supported. */ pci_write_config8(dev, 0x34, 0x70); /* Hide D3 power state and MSI capabilities */
else else
pci_write_config8(dev, 0x34, 0x50); /* set 0x61 to 0x50 if S1 is not supported. */ pci_write_config8(dev, 0x61, 0x70); /* Hide MSI capability */
byte &= ~(1 << 0); byte &= ~(1 << 0);
pci_write_config8(dev, 0x40, byte); pci_write_config8(dev, 0x40, byte);
} }