GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

soc/intel: Drop CMEM from GNVS

Browse source 
Already tagged as obsolete_cmem in <soc/nvs.h> files.

Change-Id: I8ba2a79f866fa07f1b4ae7291c72c91db5027911
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50043
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2021-01-27 21:24:08 +02:00
parent 6271dd8459
commit 22ecdbe9f3
8 changed files with 8 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/baytrail/acpi/globalnvs.asl
View file

@ -39,7 +39,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Base addresses */ /* Base addresses */
Offset (0x30), Offset (0x30),
CMEM, 32, /* 0x30 - CBMEM TOC */ , 32, /* 0x30 - CBMEM TOC */
TOLM, 32, /* 0x34 - Top of Low Memory */ TOLM, 32, /* 0x34 - Top of Low Memory */
CBMC, 32, /* 0x38 - coreboot mem console pointer */ CBMC, 32, /* 0x38 - coreboot mem console pointer */
} }

2
src/soc/intel/braswell/acpi/globalnvs.asl
View file

@ -41,7 +41,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Base addresses */ /* Base addresses */
Offset (0x30), Offset (0x30),
CMEM, 32, /* 0x30 - CBMEM TOC */ , 32, /* 0x30 - CBMEM TOC */
TOLM, 32, /* 0x34 - Top of Low Memory */ TOLM, 32, /* 0x34 - Top of Low Memory */
CBMC, 32, /* 0x38 - coreboot mem console pointer */ CBMC, 32, /* 0x38 - coreboot mem console pointer */
} }

2
src/soc/intel/broadwell/pch/acpi/globalnvs.asl
View file

@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S33G, 8, // 0x15 - Enable 3G in S3 S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State PWRS, 8, // 0x17 - AC Power State
CMEM, 32, // 0x18 - 0x1b - CBMEM TOC , 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit

2
src/soc/intel/denverton_ns/acpi/globalnvs.asl
View file

@ -38,7 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Base addresses */ /* Base addresses */
Offset (0x30), Offset (0x30),
CMEM, 32, // 0x30 - CBMEM TOC , 32, // 0x30 - CBMEM TOC
TOLM, 32, // 0x34 - Top of Low Memory TOLM, 32, // 0x34 - Top of Low Memory
CBMC, 32, // 0x38 - coreboot mem console pointer CBMC, 32, // 0x38 - coreboot mem console pointer
MMOB, 32, // 0x3c - MMIO Base Low Base MMOB, 32, // 0x3c - MMIO Base Low Base

2
src/soc/intel/skylake/acpi/globalnvs.asl
View file

@ -30,7 +30,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S33G, 8, // 0x15 - Enable 3G in S3 S33G, 8, // 0x15 - Enable 3G in S3
LIDS, 8, // 0x16 - LID State LIDS, 8, // 0x16 - LID State
PWRS, 8, // 0x17 - AC Power State PWRS, 8, // 0x17 - AC Power State
CMEM, 32, // 0x18 - 0x1b - CBMEM TOC , 32, // 0x18 - 0x1b - CBMEM TOC
CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console CBMC, 32, // 0x1c - 0x1f - coreboot Memory Console
PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit PM1I, 64, // 0x20 - 0x27 - PM1 wake status bit
GPEI, 64, // 0x28 - 0x2f - GPE wake status bit GPEI, 64, // 0x28 - 0x2f - GPE wake status bit

2
src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
View file

@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S3U0, 8, // 0x35 - Enable USB0 in S3 S3U0, 8, // 0x35 - Enable USB0 in S3
S3U1, 8, // 0x36 - Enable USB1 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3
S33G, 8, // 0x37 - Enable 3G in S3 S33G, 8, // 0x37 - Enable 3G in S3
CMEM, 32, // 0x38 - CBMEM TOC , 32, // 0x38 - CBMEM TOC
/* Integrated Graphics Device */ /* Integrated Graphics Device */
Offset (0x3c), Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1) IGDS, 8, // 0x3c - IGD state (primary = 1)

2
src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
View file

@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S3U0, 8, // 0x35 - Enable USB0 in S3 S3U0, 8, // 0x35 - Enable USB0 in S3
S3U1, 8, // 0x36 - Enable USB1 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3
S33G, 8, // 0x37 - Enable 3G in S3 S33G, 8, // 0x37 - Enable 3G in S3
CMEM, 32, // 0x38 - CBMEM TOC , 32, // 0x38 - CBMEM TOC
/* Integrated Graphics Device */ /* Integrated Graphics Device */
Offset (0x3c), Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1) IGDS, 8, // 0x3c - IGD state (primary = 1)

2
src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
View file

@ -59,7 +59,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
S3U0, 8, // 0x35 - Enable USB0 in S3 S3U0, 8, // 0x35 - Enable USB0 in S3
S3U1, 8, // 0x36 - Enable USB1 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3
S33G, 8, // 0x37 - Enable 3G in S3 S33G, 8, // 0x37 - Enable 3G in S3
CMEM, 32, // 0x38 - CBMEM TOC , 32, // 0x38 - CBMEM TOC
/* Integrated Graphics Device */ /* Integrated Graphics Device */
Offset (0x3c), Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1) IGDS, 8, // 0x3c - IGD state (primary = 1)