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mb/google/zork: Correct PIRQ_MISC0 configuration 

The current configuration is masking off IRQ 1 and IRQ 12 to the PIC.
This for some reason causes problems when using level triggered
interrupts. This change updates the PIRQ_MISC0 value to match what
skyrim is doing. This will enable level interrupts to work correctly.

BUG=b:218874489, b:160595155
TEST=Boot zork and verify keyboard still works. Boot with patch train
and verify keyboard works as expected.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2022-04-22 16:48:47 -06:00 committed by Felix Held
parent 597b9e9d71
commit 22ef1439dd
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/zork/mainboard.c
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@ -80,7 +80,7 @@ static const struct fch_irq_routing {
/* The MISC registers are not interrupt numbers */
{ PIRQ_MISC, 0xfa, 0x00 },
{ PIRQ_MISC0, 0xf1, 0x00 },
{ PIRQ_MISC0, 0x91, 0x00 },
{ PIRQ_MISC1, 0x00, 0x00 },
{ PIRQ_MISC2, 0x00, 0x00 },
};