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mb/purism/librem_mini: Fix USB_OC mapping in devicetree 

Correct USB over-current mappings in devicetree now that the
GPIO config has been fixed per schematics.

Change-Id: I564630231933c7c17a2c0a2a403fdcca9189b92e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Matt DeVillier 2020-11-04 15:32:18 -06:00 committed by Patrick Georgi
parent de10d8d609
commit 22f028a3c7
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
View File

@ -146,16 +146,16 @@ chip soc/intel/cannonlake
end
end
end
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-A front left upper
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A front left lower
register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper
register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Type-A front right lower
register "usb2_ports[4]" = "USB2_PORT_MID(OC1)" # Type-A front right upper
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth
register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left upper
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A front left lower
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper