baytrail: Update to microcode 31E and fix C-state table

With microcode 31E MWAIT 0x51 is now C6NS and 0x52 is now C6FS.

BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi, check that C1/C2/C3 are all used now

Change-Id: I8528d808f4082c85d90e2b57747d9f2e2d982b85
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178461
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4984
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)

src/soc/intel/baytrail/acpi.c

@@ -63,7 +63,7 @@ static acpi_cstate_t cstate_map[] = {
 		.ctype = 2, /* ACPI C2 */
 		.latency = 500,
 		.power = 10,
-		.resource = MWAIT_RES(5, 8),
+		.resource = MWAIT_RES(5, 1),
 	},
 	{
 		/* C6FS with full L2 shrink */

src/soc/intel/baytrail/microcode/microcode_blob.c

@@ -1,3 +1,3 @@
 unsigned microcode[] = {
-#include "M0C3067_0000031A.h"
+#include "M0C3067_0000031E.h"
 };