diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index ef7072580b..8caf0c9f1e 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -83,7 +83,6 @@ static void model_10_init(device_t dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
-
 	/* Write protect SMM space with SMMLOCK. */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 2fc943cda3..e533017ad9 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -88,7 +88,6 @@ static void model_12_init(device_t dev)
 	msr.hi &= ~(1 << (46 - 32));
 	wrmsr(NB_CFG_MSR, msr);
 
-
 	/* Write protect SMM space with SMMLOCK. */
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 5e8c9de44b..ecf1cfb968 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -34,8 +34,9 @@
 
 static void model_14_init(device_t dev)
 {
-	u32 i;
+	u8 i;
 	msr_t msr;
+	int msrno;
 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	u32 siblings;
 #endif
@@ -58,11 +59,11 @@ static void model_14_init(device_t dev)
 	/* Set shadow WB, RdMEM, WrMEM */
 	msr.lo = msr.hi = 0;
 	wrmsr (0x259, msr);
-	msr.hi = msr.lo = 0x1e1e1e1e;
+	msr.lo = msr.hi = 0x1e1e1e1e;
 	wrmsr(0x250, msr);
 	wrmsr(0x258, msr);
-	for (i = 0x268; i <= 0x26f; i++)
-		wrmsr(i, msr);
+	for (msrno = 0x268; msrno <= 0x26f; i++)
+		wrmsr(msrno, msr);
 
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
@@ -97,6 +98,7 @@ static void model_14_init(device_t dev)
 		msr.hi |= 1 << (33 - 32);
 		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
 	}
+	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
 
 	/* DisableCf8ExtCfg */
@@ -108,8 +110,6 @@ static void model_14_init(device_t dev)
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
 	wrmsr(HWCR_MSR, msr);
-
-	printk(BIOS_SPEW, "%s done.\n", __func__);
 }
 
 static struct device_operations cpu_dev_ops = {
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c
index b28ad57183..6d2bec2404 100644
--- a/src/cpu/amd/agesa/family15rl/model_15_init.c
+++ b/src/cpu/amd/agesa/family15rl/model_15_init.c
@@ -130,7 +130,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x610f31 },	  /* RL-A1 */
+	{ X86_VENDOR_AMD, 0x610f31 },	/* RL-A1 */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 5153a8b343..fa4a691b9b 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -129,8 +129,8 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x610f00 },	  /* TN-A0 */
-	{ X86_VENDOR_AMD, 0x610f31 },     /* RL-A1 (Richland) */
+	{ X86_VENDOR_AMD, 0x610f00 },   /* TN-A0 */
+	{ X86_VENDOR_AMD, 0x610f31 },   /* RL-A1 (Richland) */
 	{ 0, 0 },
 };
 
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index f62e698bdf..a8d076c2ad 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -78,7 +78,6 @@ static void model_16_init(device_t dev)
 		wrmsr(MCI_STATUS + (i * 4), msr);
 	}
 
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
 
@@ -114,7 +113,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x700f00 },	  /* KB-A0 */
+	{ X86_VENDOR_AMD, 0x700f00 },	/* KB-A0 */
 	{ 0, 0 },
 };