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mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST 

GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after
S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic
reset over PLTRST to prevent IRQ storm after S3 resume and hence
configuring GPP_D9 and GPP_D10 to use PLTRST.

BUG=b:119202293
TEST=none

Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2018-11-07 12:36:32 -08:00 committed by Patrick Georgi
parent e28d39180d
commit 230639b620
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/poppy/variants/nocturne/gpio.c
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@ -180,9 +180,9 @@ static const struct pad_config gpio_table[] = {
/* D8 : ISH_I2C1_SCL ==> NC */ /* D8 : ISH_I2C1_SCL ==> NC */
PAD_CFG_NC(GPP_D8), PAD_CFG_NC(GPP_D8),
/* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */
PAD_CFG_GPI_APIC(GPP_D9, NONE, DEEP), PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST),
/* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */
PAD_CFG_GPI_APIC(GPP_D10, NONE, DEEP), PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST),
/* D11 : ISH_SPI_MISO ==> NC */ /* D11 : ISH_SPI_MISO ==> NC */
PAD_CFG_NC(GPP_D11), PAD_CFG_NC(GPP_D11),
/* D12 : ISH_SPI_MOSI ==> NC */ /* D12 : ISH_SPI_MOSI ==> NC */