soc/amd/cezanne: add empty ramstage FCH support

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/Makefile.inc

@@ -25,6 +25,7 @@ romstage-y	+= romstage.c
 romstage-y	+= uart.c
 
 ramstage-y	+= chip.c
+ramstage-y	+= fch.c
 ramstage-y      += fsp_params.c
 ramstage-y	+= gpio.c
 ramstage-y      += reset.c

src/soc/amd/cezanne/chip.c

@@ -2,6 +2,7 @@
 
 #include <device/device.h>
 #include <fsp/api.h>
+#include <soc/southbridge.h>
 #include <types.h>
 #include "chip.h"
 
@@ -12,10 +13,13 @@ static void enable_dev(struct device *dev)
 static void soc_init(void *chip_info)
 {
 	fsp_silicon_init(false); /* no S3 support yet */
+
+	fch_init(chip_info);
 }
 
 static void soc_final(void *chip_info)
 {
+	fch_final(chip_info);
 }
 
 struct chip_operations soc_amd_cezanne_ops = {

src/soc/amd/cezanne/fch.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/southbridge.h>
+
+void fch_init(void *chip_info)
+{
+}
+
+void fch_final(void *chip_info)
+{
+}

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -30,9 +30,12 @@
 /* IO 0xf0 NCP Error */
 #define   NCP_WARM_BOOT			(1 << 7) /* Write-once */
 
-void enable_aoac_devices(void);
-void wait_for_aoac_enabled(unsigned int dev);
 void fch_pre_init(void);
 void fch_early_init(void);
+void fch_init(void *chip_info);
+void fch_final(void *chip_info);
+
+void enable_aoac_devices(void);
+void wait_for_aoac_enabled(unsigned int dev);
 
 #endif /* AMD_CEZANNE_SOUTHBRIDGE_H */