mb/google/volteer/variants/volteer: clean up gpio.c
Remove an unneccessary comment and group the variant_early_gpio_table together based on GPIO group. Changed static variable name gpio_table to override_gpio_table to be more descriptive. BUG=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: Iabe810df1e5a3df35e3543ab81b9fdb6f76c223a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42577 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -5,8 +5,7 @@
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#include <commonlib/helpers.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage */
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/* Pad configuration in ramstage */
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/* Leave eSPI pins untouched from default settings */
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static const struct pad_config override_gpio_table[] = {
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static const struct pad_config gpio_table[] = {
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/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
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/* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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PAD_CFG_GPO(GPP_A7, 1, DEEP),
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/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
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/* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */
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@ -211,31 +210,24 @@ static const struct pad_config gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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static const struct pad_config early_gpio_table[] = {
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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PAD_CFG_GPI(GPP_A17, NONE, DEEP),
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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/* B11 : PMCALERT# ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
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/* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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/* C0 : SMBCLK ==> EN_PP3300_WLAN */
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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@ -244,7 +236,6 @@ static const struct pad_config early_gpio_table[] = {
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/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
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/* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */
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PAD_CFG_GPO(GPP_F11, 1, DEEP),
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PAD_CFG_GPO(GPP_F11, 1, DEEP),
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/* F12 : GSXDOUT ==> WWAN_RST_ODL
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/* F12 : GSXDOUT ==> WWAN_RST_ODL
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To meet timing constrains - drive reset low.
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To meet timing constrains - drive reset low.
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Deasserted in ramstage. */
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Deasserted in ramstage. */
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@ -256,8 +247,8 @@ static const struct pad_config early_gpio_table[] = {
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const struct pad_config *variant_override_gpio_table(size_t *num)
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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{
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*num = ARRAY_SIZE(gpio_table);
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*num = ARRAY_SIZE(override_gpio_table);
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return gpio_table;
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return override_gpio_table;
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}
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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const struct pad_config *variant_early_gpio_table(size_t *num)
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