mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Verified that the SSDT entry matches the entry in mainboard.asl Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18343 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ID_AUTO
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_SPI_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_LPC
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select HAVE_ACPI_RESUME
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@ -1,49 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB.PCI0.SPI1)
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{
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Device (FPC)
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{
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Name (_HID, "PRP0001")
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Name (_UID, 1)
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Name (_CRS, ResourceTemplate ()
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{
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SpiSerialBus (
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0, // DeviceSelection (CS0)
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PolarityLow, // DeviceSelectionPolarity
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FourWireMode, // WireMode
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8, // DataBitLength
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ControllerInitiated, // SlaveMode
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1000000, // ConnectionSpeed (1MHz)
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ClockPolarityLow, // ClockPolarity
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ClockPhaseFirst, // ClockPhase
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"\\_SB.PCI0.SPI1", // ResourceSource
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0, // ResourceSourceIndex
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ResourceConsumer, // ResourceUsage
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)
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Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 }
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})
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Name (_DSD, Package () {
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ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
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Package () {
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Package () {
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"compatible",
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Package () { "fpc,fpc1020" }
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},
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}
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})
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}
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}
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@ -255,7 +255,15 @@ chip soc/intel/skylake
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device pci 1e.0 on end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 on end # GSPI #0
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device pci 1e.3 on end # GSPI #1
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device pci 1e.3 on
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chip drivers/spi/acpi
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""fpc,fpc1020""
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register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)"
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device spi 0 on end
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end
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end # GSPI #1
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device pci 1e.4 on end # eMMC
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device pci 1e.5 off end # SDIO
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device pci 1e.6 off end # SDCard
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@ -67,7 +67,4 @@ DefinitionBlock(
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{
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#include "acpi/dptf.asl"
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}
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/* ACPI code for EC functions */
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#include "acpi/mainboard.asl"
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}
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