mainboard/google/eve: Generate FPC device using SPI SSDT generator

Use the newly added SPI SSDT generator for adding FPC device.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl

Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/eve/Kconfig

@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ID_AUTO
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_SPI_ACPI
 	select EC_GOOGLE_CHROMEEC
 	select EC_GOOGLE_CHROMEEC_LPC
 	select HAVE_ACPI_RESUME

src/mainboard/google/eve/acpi/mainboard.asl

@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope (\_SB.PCI0.SPI1)
-{
-	Device (FPC)
-	{
-		Name (_HID, "PRP0001")
-		Name (_UID, 1)
-		Name (_CRS, ResourceTemplate ()
-		{
-			SpiSerialBus (
-				0,                   // DeviceSelection (CS0)
-				PolarityLow,         // DeviceSelectionPolarity
-				FourWireMode,        // WireMode
-				8,                   // DataBitLength
-				ControllerInitiated, // SlaveMode
-				1000000,             // ConnectionSpeed (1MHz)
-				ClockPolarityLow,    // ClockPolarity
-				ClockPhaseFirst,     // ClockPhase
-				"\\_SB.PCI0.SPI1",   // ResourceSource
-				0,                   // ResourceSourceIndex
-				ResourceConsumer,    // ResourceUsage
-			)
-			Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 }
-		})
-		Name (_DSD, Package () {
-			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
-			Package () {
-				Package () {
-					"compatible",
-					Package () { "fpc,fpc1020" }
-				},
-			}
-		})
-	}
-}

src/mainboard/google/eve/devicetree.cb

@@ -255,7 +255,15 @@ chip soc/intel/skylake
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 on  end # GSPI #0
-		device pci 1e.3 on  end # GSPI #1
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "uid" = "1"
+				register "compat_string" = ""fpc,fpc1020""
+				register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #1
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 off end # SDCard

src/mainboard/google/eve/dsdt.asl

@@ -67,7 +67,4 @@ DefinitionBlock(
 	{
 		#include "acpi/dptf.asl"
 	}
-
-	/* ACPI code for EC functions */
-	#include "acpi/mainboard.asl"
 }