enable apic ext id
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a734f53721
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@ -150,6 +150,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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//#include "northbridge/amd/amdk8/setup_resource_map.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#if 1
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#define ENABLE_APIC_EXT_ID 1
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#define APIC_ID_OFFSET 0x10
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#else
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#define ENABLE_APIC_EXT_ID 0
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#endif
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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@ -228,23 +235,22 @@ static void main(unsigned long bist)
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};
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int i;
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int needs_reset;
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unsigned nodeid;
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if (bist == 0) {
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/* Skip this if there was a built in self test failure */
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amd_early_mtrr_init();
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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#if 1
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nodeid = lapicid() & 0xf;
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#if ENABLE_APIC_EXT_ID == 1
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enable_apic_ext_id(nodeid);
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lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
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#endif
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if (cpu_init_detected(nodeid)) {
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asm volatile ("jmp __cpu_reset");
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#else
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/* cpu reset also reset the memtroller ????
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need soft_reset to reset all except keep HT link freq and width */
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distinguish_cpu_resets();
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soft2_reset();
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#endif
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}
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distinguish_cpu_resets();
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distinguish_cpu_resets(nodeid);
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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@ -259,7 +265,12 @@ static void main(unsigned long bist)
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setup_s4882_resource_map();
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needs_reset = setup_coherent_ht_domain();
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#if 0
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
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#else
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// automatically set that for you, but you might meet tight space
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needs_reset |= ht_setup_chains_x();
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#endif
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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@ -133,6 +133,23 @@ static void disable_probes(void)
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}
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#ifndef ENABLE_APIC_EXT_ID
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#define ENABLE_APIC_EXT_ID 0
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#endif
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static void enable_apic_ext_id(u8 node)
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{
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#if ENABLE_APIC_EXT_ID==1
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#warning "FIXME Is the right place to enable apic ext id here?"
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u32 val;
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val = pci_read_config32(NODE_HT(node), 0x68);
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val |= HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST ;
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pci_write_config32(NODE_HT(node), 0x68, val);
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#endif
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}
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static void enable_routing(u8 node)
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{
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u32 val;
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@ -715,6 +715,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
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{
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struct bus *cpu_bus;
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int i;
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int apic_id_offset = lapicid(); // bsp apicid
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/* Find which cpus are present */
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cpu_bus = &dev->link[0];
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@ -749,6 +750,9 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
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/* Report what I have done */
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if (cpu) {
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if(cpu->path.u.apic.apic_id<apic_id_offset) {
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cpu->path.u.apic.apic_id += apic_id_offset;
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}
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printk_debug("CPU: %s %s\n", dev_path(cpu),
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cpu->enabled?"enabled":"disabled");
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}
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@ -7,12 +7,12 @@
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static int cpu_init_detected(void)
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static int cpu_init_detected(unsigned nodeid)
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{
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unsigned long htic;
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device_t dev;
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dev = PCI_DEV(0, 0x18 + lapicid(), 0);
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dev = PCI_DEV(0, 0x18 + nodeid, 0);
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htic = pci_read_config32(dev, HT_INIT_CONTROL);
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return !!(htic & HTIC_INIT_Detect);
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@ -34,11 +34,11 @@ static int cold_reset_detected(void)
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return !(htic & HTIC_ColdR_Detect);
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}
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static void distinguish_cpu_resets(void)
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static void distinguish_cpu_resets(unsigned nodeid)
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{
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uint32_t htic;
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device_t device;
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device = PCI_DEV(0, 0x18 + lapicid(), 0);
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device = PCI_DEV(0, 0x18 + nodeid, 0);
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htic = pci_read_config32(device, HT_INIT_CONTROL);
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htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
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pci_write_config32(device, HT_INIT_CONTROL, htic);
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