enable apic ext id

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/tyan/s4882/auto.c

@@ -150,6 +150,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 //#include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/raminit.c"
 
+#if 1
+        #define ENABLE_APIC_EXT_ID 1
+        #define APIC_ID_OFFSET 0x10
+#else
+        #define ENABLE_APIC_EXT_ID 0
+#endif
+
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
@@ -228,23 +235,22 @@ static void main(unsigned long bist)
 	};
 	int i;
         int needs_reset;
+	unsigned nodeid;
         if (bist == 0) {
                 /* Skip this if there was a built in self test failure */
                 amd_early_mtrr_init();
                 enable_lapic();
                 init_timer();
-
+                nodeid = lapicid() & 0xf;
-                if (cpu_init_detected()) {
+        #if ENABLE_APIC_EXT_ID == 1
-#if 1
+                enable_apic_ext_id(nodeid);
-                        asm volatile ("jmp __cpu_reset");
+                lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
-#else                   
-                /* cpu reset also reset the memtroller ????
-                        need soft_reset to reset all except keep HT link freq and width */
-                        distinguish_cpu_resets();
-                        soft2_reset();
         #endif
+                if (cpu_init_detected(nodeid)) {
+                        asm volatile ("jmp __cpu_reset");
                 }
-                distinguish_cpu_resets();
+                distinguish_cpu_resets(nodeid);
+
                 if (!boot_cpu()) {
                         stop_this_cpu();
                 }       
@@ -259,7 +265,12 @@ static void main(unsigned long bist)
 
         setup_s4882_resource_map();
         needs_reset = setup_coherent_ht_domain();
+#if 0
         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
+#else
+        // automatically set that for you, but you might meet tight space
+        needs_reset |= ht_setup_chains_x();
+#endif
         if (needs_reset) {
                 print_info("ht reset -\r\n");
                 soft_reset();

src/northbridge/amd/amdk8/coherent_ht.c

@@ -133,6 +133,23 @@ static void disable_probes(void)
 
 }
 
+#ifndef ENABLE_APIC_EXT_ID
+#define ENABLE_APIC_EXT_ID 0 
+#endif
+
+static void enable_apic_ext_id(u8 node)
+{
+#if ENABLE_APIC_EXT_ID==1
+#warning "FIXME Is the right place to enable apic ext id here?"
+
+        u32 val;
+
+        val = pci_read_config32(NODE_HT(node), 0x68);
+        val |= HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST ;
+        pci_write_config32(NODE_HT(node), 0x68, val);
+#endif
+}
+
 static void enable_routing(u8 node)
 {
 	u32 val;

src/northbridge/amd/amdk8/northbridge.c

@@ -715,6 +715,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 {
 	struct bus *cpu_bus;
 	int i;
+	int apic_id_offset = lapicid(); // bsp apicid
 
 	/* Find which cpus are present */
 	cpu_bus = &dev->link[0];
@@ -749,6 +750,9 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 		
 		/* Report what I have done */
 		if (cpu) {
+                        if(cpu->path.u.apic.apic_id<apic_id_offset) {
+                                cpu->path.u.apic.apic_id += apic_id_offset;
+                        }  
 			printk_debug("CPU: %s %s\n", dev_path(cpu),
 				     cpu->enabled?"enabled":"disabled");
 		}

src/northbridge/amd/amdk8/reset_test.c

@@ -7,12 +7,12 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static int cpu_init_detected(void)
+static int cpu_init_detected(unsigned nodeid)
 {
 	unsigned long htic;
 	device_t dev;
 
-	dev = PCI_DEV(0, 0x18 + lapicid(), 0);
+	dev = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(dev, HT_INIT_CONTROL);
 
 	return !!(htic & HTIC_INIT_Detect);
@@ -34,11 +34,11 @@ static int cold_reset_detected(void)
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static void distinguish_cpu_resets(void)
+static void distinguish_cpu_resets(unsigned nodeid)
 {
 	uint32_t htic;
 	device_t device;
-	device = PCI_DEV(0, 0x18 + lapicid(), 0);
+	device = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(device, HT_INIT_CONTROL);
 	htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
 	pci_write_config32(device, HT_INIT_CONTROL, htic);