soc/amd/stoneyridge: implement and use get_pstate_0_reg
Introduce get_pstate_0_reg and use it in tsc_freq_mhz to get the P state register number corresponding to P state 0. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b92a858bf36b04a570d99c656e5ccfc84457724 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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@ -15,6 +15,7 @@
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#include <soc/cpu.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <types.h>
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/*
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/*
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* MP and SMM loading initialization.
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* MP and SMM loading initialization.
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@ -69,3 +70,8 @@ static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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.id_table = cpu_table,
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};
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};
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uint32_t get_pstate_0_reg(void)
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{
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return (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
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}
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@ -12,7 +12,6 @@
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unsigned long tsc_freq_mhz(void)
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unsigned long tsc_freq_mhz(void)
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{
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{
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union pstate_msr pstate_reg;
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union pstate_msr pstate_reg;
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uint8_t boost_states;
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/*
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/*
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* See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
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* See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
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@ -20,10 +19,7 @@ unsigned long tsc_freq_mhz(void)
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* to the "Software P-state Numbering" section, P0 is the highest
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* to the "Software P-state Numbering" section, P0 is the highest
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* non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
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* non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
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*/
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*/
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boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
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pstate_reg.raw = rdmsr(PSTATE_MSR(get_pstate_0_reg())).raw;
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>> 2) & 0x7;
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pstate_reg.raw = rdmsr(PSTATE_MSR(boost_states)).raw;
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if (!pstate_reg.pstate_en)
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if (!pstate_reg.pstate_en)
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die("Unknown error: cannot determine P-state 0\n");
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die("Unknown error: cannot determine P-state 0\n");
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