GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/stoneyridge: implement and use get_pstate_0_reg 

Introduce get_pstate_0_reg and use it in tsc_freq_mhz to get the P state
register number corresponding to P state 0.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b92a858bf36b04a570d99c656e5ccfc84457724
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held 2023-03-25 02:51:41 +01:00
parent 52742b6dbd
commit 2323acab6a
2 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/stoneyridge/cpu.c
View File

@ -15,6 +15,7 @@
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <console/console.h>
#include <types.h>
/*
* MP and SMM loading initialization.
@ -69,3 +70,8 @@ static const struct cpu_driver model_15 __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};
uint32_t get_pstate_0_reg(void)
{
return (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
}

6
src/soc/amd/stoneyridge/tsc_freq.c
View File

@ -12,7 +12,6 @@
unsigned long tsc_freq_mhz(void)
{
union pstate_msr pstate_reg;
uint8_t boost_states;
/*
* See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for
@ -20,10 +19,7 @@ unsigned long tsc_freq_mhz(void)
* to the "Software P-state Numbering" section, P0 is the highest
* non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)).
*/
boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL)
>> 2) & 0x7;
pstate_reg.raw = rdmsr(PSTATE_MSR(boost_states)).raw;
pstate_reg.raw = rdmsr(PSTATE_MSR(get_pstate_0_reg())).raw;
if (!pstate_reg.pstate_en)
die("Unknown error: cannot determine P-state 0\n");