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soc/intel/braswell: Clean up devicetree settings 

Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.

Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Angel Pons 2020-12-11 17:20:16 +01:00
parent 68cf57cf33
commit 233ae1919b
8 changed files with 11 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/facebook/fbg1701/devicetree.cb
View File

@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "1"
register "PcdEmmcMode" = "PCH_PCI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"

10
src/mainboard/google/cyan/devicetree.cb
View File

@ -7,14 +7,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "1"
register "PcdCaMirrorEn" = "1"
@ -40,9 +35,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_PCI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@ -68,9 +60,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "1"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"

10
src/mainboard/intel/strago/devicetree.cb
View File

@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "1"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_ACPI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "0" # Disable SATA
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"

10
src/mainboard/portwell/m107/devicetree.cb
View File

@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "0" # Enable SVID
register "ChvSvidConfig" = "1"
register "PcdEmmcMode" = "PCH_PCI_MODE"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "1"
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "5"
@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"

10
src/mainboard/protectli/vault_bsw/devicetree.cb
View File

@ -4,14 +4,9 @@ chip soc/intel/braswell
# Set the parameters for MemoryInit
############################################################
register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB
register "PcdMrcInitMmioSize" = "0x0800"
register "PcdMrcInitSpdAddr1" = "0xa0"
register "PcdMrcInitSpdAddr2" = "0xa2"
register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB"
register "PcdApertureSize" = "2"
register "PcdGttSize" = "1"
register "PcdDvfsEnable" = "0"
register "PcdCaMirrorEn" = "1"
@ -37,9 +32,6 @@ chip soc/intel/braswell
register "PunitPwrConfigDisable" = "1" # Disable SVID
register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
register "PcdEmmcMode" = "PCH_DISABLED"
register "PcdUsb3ClkSsc" = "1"
register "PcdDispClkSsc" = "1"
register "PcdSataClkSsc" = "1"
register "PcdEnableSata" = "1"
register "Usb2Port0PerPortPeTxiSet" = "7"
register "Usb2Port0PerPortTxiSet" = "6"
@ -65,9 +57,7 @@ chip soc/intel/braswell
register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"
register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"
register "PcdSataInterfaceSpeed" = "3"
register "PcdPchSsicEnable" = "1"
register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM
register "PMIC_I2CBus" = "0"
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"

12
src/soc/intel/braswell/chip.c
View File

@ -81,9 +81,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->ChvSvidConfig = config->ChvSvidConfig;
params->DptfDisable = config->DptfDisable;
params->PcdEmmcMode = config->PcdEmmcMode;
params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
params->PcdDispClkSsc = config->PcdDispClkSsc;
params->PcdSataClkSsc = config->PcdSataClkSsc;
params->PcdUsb3ClkSsc = 1;
params->PcdDispClkSsc = 1;
params->PcdSataClkSsc = 1;
params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
@ -115,14 +115,14 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5;
params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5;
params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
params->PcdSataInterfaceSpeed = 3;
params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
params->PcdPcieRootPortSpeed = 0;
params->PcdPchSsicEnable = config->PcdPchSsicEnable;
params->PcdLogoPtr = config->PcdLogoPtr;
params->PcdLogoSize = config->PcdLogoSize;
params->PcdRtcLock = config->PcdRtcLock;
params->PcdRtcLock = 0;
params->PMIC_I2CBus = config->PMIC_I2CBus;
params->ISPEnable = config->ISPEnable;
params->ISPPciDevConfig = config->ISPPciDevConfig;

12
src/soc/intel/braswell/chip.h
View File

@ -41,7 +41,6 @@ enum usb_comp_bg_value {
struct soc_intel_braswell_config {
uint8_t enable_xdp_tap;
uint8_t clkreq_enable;
enum serirq_mode serirq_mode;
@ -75,14 +74,9 @@ struct soc_intel_braswell_config {
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
* These are configuration values that are passed to FSP during MemoryInit.
*/
uint16_t PcdMrcInitTsegSize;
uint16_t PcdMrcInitMmioSize;
uint8_t PcdMrcInitSpdAddr1;
uint8_t PcdMrcInitSpdAddr2;
uint8_t PcdIgdDvmt50PreAlloc;
uint8_t PcdApertureSize;
uint8_t PcdGttSize;
uint8_t PcdLegacySegDecode;
uint8_t PcdDvfsEnable;
uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */
@ -110,9 +104,6 @@ struct soc_intel_braswell_config {
uint8_t ChvSvidConfig;
uint8_t DptfDisable;
uint8_t PcdEmmcMode;
uint8_t PcdUsb3ClkSsc;
uint8_t PcdDispClkSsc;
uint8_t PcdSataClkSsc;
uint8_t Usb2Port0PerPortPeTxiSet;
uint8_t Usb2Port0PerPortTxiSet;
uint8_t Usb2Port0IUsbTxEmphasisEn;
@ -137,14 +128,11 @@ struct soc_intel_braswell_config {
uint8_t Usb3Lane1Ow2tapgen2deemph3p5;
uint8_t Usb3Lane2Ow2tapgen2deemph3p5;
uint8_t Usb3Lane3Ow2tapgen2deemph3p5;
uint8_t PcdSataInterfaceSpeed;
uint8_t PcdPchUsbSsicPort;
uint8_t PcdPchUsbHsicPort;
uint8_t PcdPcieRootPortSpeed;
uint8_t PcdPchSsicEnable;
uint32_t PcdLogoPtr;
uint32_t PcdLogoSize;
uint8_t PcdRtcLock;
uint8_t PMIC_I2CBus;
uint8_t ISPEnable;
uint8_t ISPPciDevConfig;

10
src/soc/intel/braswell/romstage/romstage.c
View File

@ -113,14 +113,14 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd
config = config_of(dev);
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0;
upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0;
upd->PcdMrcInitMmioSize = 0x800;
upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;
upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
upd->PcdApertureSize = config->PcdApertureSize;
upd->PcdGttSize = config->PcdGttSize;
upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
upd->PcdApertureSize = 2;
upd->PcdGttSize = 1;
upd->PcdLegacySegDecode = 0;
upd->PcdDvfsEnable = config->PcdDvfsEnable;
upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
}