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soc/intel/cannonlake: Allow to configure maximum package C state 

Sometimes it's preferable or even necessary (e.g. stability issues) to
limit the maximum package C state. Let's add a devicetree option that
keeps the current behavior if it is left unset.

Change-Id: I0dc254d34f46de4c65cb85cc92e4b7f26618888d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber 2021-07-27 10:26:31 +00:00 committed by Paul Fagerburg
parent e4bc55b843
commit 234e7ecb29
2 changed files with 21 additions and 2 deletions
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13
src/soc/intel/cannonlake/chip.h
View File

@ -64,6 +64,19 @@ struct soc_intel_cannonlake_config {
/* Enable DPTF support */
int dptf_enable;
enum {
MAX_PC_DEFAULT = 0,
MAX_PC0_1 = 1,
MAX_PC2 = 2,
MAX_PC3 = 3,
MAX_PC6 = 4,
MAX_PC7 = 5,
MAX_PC7S = 6,
MAX_PC8 = 7,
MAX_PC9 = 8,
MAX_PC10 = 9,
} max_package_c_state;
/* Deep SX enable for both AC and DC */
int deep_s3_enable_ac;
int deep_s3_enable_dc;

10
src/soc/intel/cannonlake/cpu.c
View File

@ -55,10 +55,16 @@ static void configure_misc(void)
wrmsr(MSR_POWER_CTL, msr);
}
static void configure_c_states(void)
static void configure_c_states(const config_t *const cfg)
{
msr_t msr;
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
if (cfg->max_package_c_state && (msr.lo & 0xf) >= cfg->max_package_c_state) {
msr.lo = (msr.lo & ~0xf) | ((cfg->max_package_c_state - 1) & 0xf);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
}
/* C-state Interrupt Response Latency Control 1 - package C6/C7 short */
msr.hi = 0;
msr.lo = IRTL_VALID | IRTL_32768_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
@ -104,7 +110,7 @@ void soc_core_init(struct device *cpu)
setup_lapic();
/* Configure c-state interrupt response time */
configure_c_states();
configure_c_states(cfg);
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();