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soc/intel: drop P_BLK support 

P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.

For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.

Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Michael Niewöhner 2021-10-04 16:59:49 +02:00
parent 51254ee939
commit 2353cd9936
14 changed files with 9 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/apollolake/acpi.c
View File

@ -122,11 +122,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->pm_tmr_len = 4;
fadt->duty_width = 3;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;

8
src/soc/intel/baytrail/acpi.c
View File

@ -272,17 +272,11 @@ static void generate_p_state_entries(int core, int cores_per_package)
void generate_cpu_entries(const struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
for (core = 0; core < pattrs->num_cpus; core++) {
if (core > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_SB.CPUx */
acpigen_write_processor(core, pcontrol_blk, plen);
acpigen_write_processor(core, 0, 0);
/* Generate P-state tables */
generate_p_state_entries(core, pattrs->num_cpus);

6
src/soc/intel/baytrail/fadt.c
View File

@ -30,16 +30,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_PLATFORM_CLOCK;

8
src/soc/intel/braswell/acpi.c
View File

@ -280,17 +280,11 @@ static void generate_p_state_entries(int core, int cores_per_package)
void generate_cpu_entries(const struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
for (core = 0; core < pattrs->num_cpus; core++) {
if (core > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_SB.CPUx */
acpigen_write_processor(core, pcontrol_blk, plen);
acpigen_write_processor(core, 0, 0);
/* Generate P-state tables */
generate_p_state_entries(core, pattrs->num_cpus);

6
src/soc/intel/braswell/fadt.c
View File

@ -30,16 +30,12 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_PLATFORM_CLOCK;

5
src/soc/intel/broadwell/pch/fadt.c
View File

@ -29,11 +29,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 32;
/* P_LVLx not used */
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;

14
src/soc/intel/common/block/acpi/acpi.c
View File

@ -145,11 +145,10 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
/* GPE0 STS/EN pairs each 32 bits wide. */
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->duty_offset = 1;
fadt->day_alrm = 0xd;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_PLATFORM_CLOCK;
@ -398,8 +397,7 @@ __weak void soc_power_states_generation(int core_id,
void generate_cpu_entries(const struct device *device)
{
int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS;
int plen = 6;
int core_id, cpu_id;
int totalcores = dev_count_cpu();
unsigned int num_virt;
unsigned int num_phys;
@ -413,14 +411,8 @@ void generate_cpu_entries(const struct device *device)
for (cpu_id = 0; cpu_id < numcpus; cpu_id++) {
for (core_id = 0; core_id < num_virt; core_id++) {
if (core_id > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_SB.CPUx */
acpigen_write_processor((cpu_id) * num_virt +
core_id, pcontrol_blk, plen);
acpigen_write_processor((cpu_id) * num_virt + core_id, 0, 0);
/* Generate C-state tables */
generate_c_state_entries();

3
src/soc/intel/denverton_ns/acpi.c
View File

@ -102,9 +102,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
/* PM2 Control Registers */

1
src/soc/intel/denverton_ns/include/soc/msr.h
View File

@ -7,7 +7,6 @@
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_FEATURE_CONFIG 0x13c
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
#define FEATURE_CONFIG_LOCK (1 << 0)

3
src/soc/intel/elkhartlake/acpi.c
View File

@ -160,9 +160,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
fadt->x_pm_tmr_blk.addrh = 0x0;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_width = 0x3; /* CLK_VAL bits 3:1 */
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;

6
src/soc/intel/skylake/fadt.c
View File

@ -34,10 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
/* There are 4 GPE0 STS/EN pairs each 32 bits wide. */
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;
fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
@ -45,7 +41,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->iapc_boot_arch |= ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
ACPI_FADT_PLATFORM_CLOCK;

9
src/soc/intel/xeon_sp/include/soc/msr.h
View File

@ -28,18 +28,9 @@
/* No package C-state limit. All C-States supported by the processor are available. */
#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT)
#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT)
#define IO_MWAIT_REDIRECTION_SHIFT 10
#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT)
#define CFG_LOCK_SHIFT 15
#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT)
/* MSR_PMG_IO_CAPTURE_BASE bits */
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */
#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT)
#define CST_RANGE_SHIFT 16 /* 18:16 bits */
#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT)
/* MSR_POWER_CTL bits */
#define MSR_POWER_CTL 0x1fc
#define BIDIR_PROCHOT_ENABLE_SHIFT 0

7
src/soc/intel/xeon_sp/skx/cpu.c
View File

@ -54,14 +54,9 @@ static void xeon_sp_core_init(struct device *cpu)
/* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/
msr.hi = 0;
msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE);
msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* set MSR_PMG_IO_CAPTURE_BASE - scope per core */
msr.hi = 0;
msr.lo = (LVL_2_BASE_ADDRESS | CST_RANGE_MAX_C6);
wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
/* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */
msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE

5
src/soc/intel/xeon_sp/skx/soc_acpi.c
View File

@ -48,11 +48,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->duty_width = 0;
/* RTC Registers */
fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;