exynos/snow: get rid of board-specific arbitration code
Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and EC can act as a master, so to avoid conflicts an arbitration mechanism consisting of two GPIOs is used. By default, the AP "owns" the bus unless it is off (in which case the EC doesn't monitor the arbitration pins). This means the boot firmware does not need to worry about these lines. The payload may if it needs to communicate with the EC, though. In any case, board-specific bus arbitration logic does not belong in a low-level driver that is supposed to be generic for an entire CPU family. If the payload needs to talk to the EC, we'll deal with it there. Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -91,8 +91,4 @@ struct spl_machine_param *spl_get_machine_params(void);
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*/
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void spl_early_init(void);
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/* FIXME(dhendrix): for early i2c init */
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void board_i2c_release_bus(int node);
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int board_i2c_claim_bus(int node);
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#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
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@ -39,9 +39,6 @@
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#include "device/i2c.h"
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#include "s3c24x0_i2c.h"
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/* for board_i2c_* */
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#include "cpu/samsung/exynos5-common/spl.h"
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#define I2C_WRITE 0
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#define I2C_READ 1
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@ -531,12 +528,7 @@ int i2c_probe(uchar chip)
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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if (board_i2c_claim_bus(i2c->node)) {
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debug("I2C cannot claim bus %d\n", i2c->bus_num);
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return -1;
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}
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ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, 0, 0, buf, 1);
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board_i2c_release_bus(i2c->node);
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return ret != I2C_OK;
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}
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@ -578,13 +570,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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i2c = get_bus(g_current_bus);
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if (!i2c)
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return -1;
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if (board_i2c_claim_bus(i2c->node)) {
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debug("I2C cannot claim bus %d\n", i2c->bus_num);
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return -1;
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}
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ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
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alen, buffer, len);
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board_i2c_release_bus(i2c->node);
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if (ret) {
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debug("I2c read: failed %d\n", ret);
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return 1;
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@ -628,13 +615,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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i2c = get_bus(g_current_bus);
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if (!i2c)
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return -1;
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if (board_i2c_claim_bus(i2c->node)) {
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debug("I2C cannot claim bus %d\n", i2c->bus_num);
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return -1;
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}
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ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen],
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alen, buffer, len);
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board_i2c_release_bus(i2c->node);
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return ret != 0;
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}
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@ -649,15 +649,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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#endif
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if (!i2c)
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return -1;
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#if 0
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if (board_i2c_claim_bus(i2c->node)) {
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debug("I2C cannot claim bus %d\n", i2c->bus_num);
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return -1;
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}
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#endif
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ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen],
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alen, buffer, len);
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//board_i2c_release_bus(i2c->node);
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if (ret) {
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//debug("I2c read: failed %d\n", ret);
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return 1;
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@ -702,15 +695,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
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i2c = &i2c0;
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if (!i2c)
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return -1;
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#if 0
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if (board_i2c_claim_bus(i2c->node)) {
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//debug("I2C cannot claim bus %d\n", i2c->bus_num);
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return -1;
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}
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#endif
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ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen],
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alen, buffer, len);
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//board_i2c_release_bus(i2c->node);
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return ret != 0;
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}
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@ -87,18 +87,3 @@ int board_wakeup_permitted(void)
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return !is_bad_wake;
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}
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/*
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* TODO(sjg@chromium.org):
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* Declared there here for SPL, since there is no core i2c subsystem and
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* cmd_i2c.c is not included.
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*/
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void board_i2c_release_bus(int node)
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{
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}
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int board_i2c_claim_bus(int node)
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{
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/* EC is not allowed to touch the bus until we enter U-Boot */
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return 0;
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}
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