soc/intel/broadwell: Add int to unsigned

Fix the following issue detected by checkpatch:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'

TEST=None

Change-Id: Iae22e724b6adae16248db7dc8f822f65bfadae5f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18873
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>

src/soc/intel/broadwell/bootblock/cpu.c

@@ -24,9 +24,8 @@
 #include <soc/rcba.h>
 #include <soc/msr.h>
 
-static void set_var_mtrr(
-	unsigned reg, unsigned base, unsigned size, unsigned type)
-
+static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
+	unsigned int type)
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
 	msr_t basem, maskm;

src/soc/intel/broadwell/chip.c

@@ -61,7 +61,8 @@ struct chip_operations soc_intel_broadwell_ops = {
 	.init       = &broadwell_init_pre_device,
 };
 
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(device_t dev, unsigned int vendor,
+	unsigned int device)
 {
 	if (!vendor || !device)
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,

src/soc/intel/broadwell/cpu.c

@@ -323,8 +323,8 @@ void set_power_limits(u8 power_limit_1_time)
 {
 	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
 	msr_t limit;
-	unsigned power_unit;
-	unsigned tdp, min_power, max_power, max_time;
+	unsigned int power_unit;
+	unsigned int tdp, min_power, max_power, max_time;
 	u8 power_limit_1_val;
 
 	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))

src/soc/intel/broadwell/ehci.c

@@ -24,7 +24,8 @@
 #include <soc/ehci.h>
 #include <soc/pch.h>
 
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned int vendor,
+	unsigned int device)
 {
 	u8 access_cntl;
 

src/soc/intel/broadwell/gpio.c

@@ -161,11 +161,11 @@ int get_gpio(int gpio_num)
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
 {
 	int gpio;
-	unsigned bitmask = 1;
-	unsigned vector = 0;
+	unsigned int bitmask = 1;
+	unsigned int vector = 0;
 
 	while (bitmask &&
 	       ((gpio = *gpio_num_array++) != -1)) {

src/soc/intel/broadwell/igd.c

@@ -277,7 +277,7 @@ static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
 
 static int gtt_poll(u32 reg, u32 mask, u32 value)
 {
-	unsigned try = GT_RETRY;
+	unsigned int try = GT_RETRY;
 	u32 data;
 
 	while (try--) {

src/soc/intel/broadwell/include/soc/gpio.h

@@ -186,6 +186,6 @@ int gpio_is_native(int gpio_num);
  * Get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
 
 #endif

src/soc/intel/broadwell/include/soc/romstage.h

@@ -48,7 +48,7 @@ void pch_uart_init(void);
 void intel_early_me_status(void);
 
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 
 int early_spi_read(u32 offset, u32 size, u8 *buffer);
 int early_spi_read_wpsr(u8 *sr);

src/soc/intel/broadwell/include/soc/smbus.h

@@ -40,9 +40,9 @@
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 #define SMBUS_SLAVE_ADDR	0x24
 
-int do_smbus_read_byte(unsigned smbus_base, unsigned device,
-		       unsigned address);
-int do_smbus_write_byte(unsigned smbus_base, unsigned device,
-			unsigned address, unsigned data);
+int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
+		       unsigned int address);
+int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
+			unsigned int address, unsigned int data);
 
 #endif

src/soc/intel/broadwell/iobp.c

@@ -23,7 +23,7 @@
 
 static inline int iobp_poll(void)
 {
-	unsigned try;
+	unsigned int try;
 
 	for (try = IOBP_RETRY; try > 0; try--) {
 		u16 status = RCBA16(IOBPS);

src/soc/intel/broadwell/me.c

@@ -149,7 +149,7 @@ static inline u32 read_cb(void)
 static int mei_wait_for_me_ready(void)
 {
 	struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
 
 	while (try--) {
 		read_me_csr(&me);
@@ -189,7 +189,7 @@ static void mei_reset(void)
 static int mei_send_packet(struct mei_header *mei, void *req_data)
 {
 	struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
 	u32 *data;
 
 	/* Number of dwords to write */
@@ -293,8 +293,8 @@ static int mei_recv_msg(void *header, int header_bytes,
 {
 	struct mei_header mei_rsp;
 	struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
 	u32 *data;
 
 	/* Total number of dwords to read from circular buffer */

src/soc/intel/broadwell/pcie.c

@@ -186,7 +186,7 @@ static void root_port_init_config(device_t dev)
 static void pch_pcie_device_set_func(int index, int pci_func)
 {
 	device_t dev;
-	unsigned new_devfn;
+	unsigned int new_devfn;
 
 	dev = rpc.ports[index];
 
@@ -638,7 +638,8 @@ static void pch_pcie_enable(device_t dev)
 		root_port_commit_config();
 }
 
-static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pcie_set_subsystem(device_t dev, unsigned int vendor,
+	unsigned int device)
 {
 	/* NOTE: This is not the default position! */
 	if (!vendor || !device)

src/soc/intel/broadwell/romstage/smbus.c

@@ -44,7 +44,7 @@ void enable_smbus(void)
 	reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
 }

src/soc/intel/broadwell/smbus_common.c

@@ -32,7 +32,7 @@ static void smbus_delay(void)
 
 static int smbus_wait_until_ready(u16 smbus_base)
 {
-	unsigned loops = SMBUS_TIMEOUT;
+	unsigned int loops = SMBUS_TIMEOUT;
 	unsigned char byte;
 	do {
 		smbus_delay();
@@ -45,7 +45,7 @@ static int smbus_wait_until_ready(u16 smbus_base)
 
 static int smbus_wait_until_done(u16 smbus_base)
 {
-	unsigned loops = SMBUS_TIMEOUT;
+	unsigned int loops = SMBUS_TIMEOUT;
 	unsigned char byte;
 	do {
 		smbus_delay();
@@ -56,7 +56,8 @@ static int smbus_wait_until_done(u16 smbus_base)
 	return loops ? 0 : -1;
 }
 
-int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
+	unsigned int address)
 {
 	unsigned char global_status_register;
 	unsigned char byte;
@@ -102,8 +103,8 @@ int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
 	return byte;
 }
 
-int do_smbus_write_byte(unsigned smbus_base, unsigned device,
-			unsigned address, unsigned data)
+int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
+			unsigned int address, unsigned int data)
 {
 	unsigned char global_status_register;
 

src/soc/intel/broadwell/spi.c

@@ -102,7 +102,7 @@ typedef struct ich_spi_controller {
 	uint16_t *optype;
 	uint32_t *addr;
 	uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
 	uint8_t *status;
 	uint16_t *control;
 	uint32_t *bbar;
@@ -166,7 +166,7 @@ static u8 readb_(const void *addr)
 {
 	u8 v = read8(addr);
 	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -174,7 +174,7 @@ static u16 readw_(const void *addr)
 {
 	u16 v = read16(addr);
 	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -182,7 +182,7 @@ static u32 readl_(const void *addr)
 {
 	u32 v = read32(addr);
 	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -190,21 +190,21 @@ static void writeb_(u8 b, const void *addr)
 {
 	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
 	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, const void *addr)
 {
 	write32(addr, b);
 	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
@@ -307,13 +307,13 @@ typedef struct spi_transaction {
 	uint32_t offset;
 } spi_transaction;
 
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
 	trans->out += bytes;
 	trans->bytesout -= bytes;
 }
 
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
 	trans->in += bytes;
 	trans->bytesin -= bytes;