zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
c30a6e859e
commit
23836e2345
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@ -1,4 +1,5 @@
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#define DEBUG_PLL 0
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#define DEBUG_PLL 0
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#define PLL_CRTC_DECODE 0
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/* FIXME: remove the FAIL definition */
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/* FIXME: remove the FAIL definition */
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#if 0
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#if 0
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@ -123,9 +124,7 @@ static int aty_valid_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
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#if DEBUG_PLL==1
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#if DEBUG_PLL==1
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int pllmclk, pllsclk;
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int pllmclk, pllsclk;
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#endif
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#endif
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u32 q;
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u32 q, x; /* x is a workaround for sparc64-linux-gcc */
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x = x; /* x is a workaround for sparc64-linux-gcc */
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pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;
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pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per;
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@ -485,12 +485,12 @@ static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
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static void ati_ragexl_init(device_t dev)
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static void ati_ragexl_init(device_t dev)
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{
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{
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u32 chip_id;
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u32 chip_id;
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u32 i;
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int j;
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int j;
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u16 type;
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u16 type;
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u8 rev;
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u8 rev;
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const char *chipname = NULL;
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const char *chipname = NULL;
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#if CONFIG_CONSOLE_BTEXT
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#if CONFIG_CONSOLE_BTEXT
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u32 i;
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const char *xtal;
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const char *xtal;
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#endif
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#endif
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int pll, mclk, xclk;
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int pll, mclk, xclk;
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@ -2,6 +2,7 @@
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#define BOOT_TABLES_H
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#define BOOT_TABLES_H
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#include <boot/coreboot_tables.h>
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#include <boot/coreboot_tables.h>
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#include <arch/coreboot_tables.h>
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void lb_add_memory_range(struct lb_memory *mem,
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void lb_add_memory_range(struct lb_memory *mem,
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uint32_t type, uint64_t start, uint64_t size);
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uint32_t type, uint64_t start, uint64_t size);
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@ -21,12 +21,11 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <boot/tables.h>
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#include <arch/coreboot_tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <../southbridge/amd/sb600/sb600.h>
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#include <southbridge/amd/sb600/sb600.h>
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#include "chip.h"
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#include "chip.h"
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#define ADT7461_ADDRESS 0x4C
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#define ADT7461_ADDRESS 0x4C
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@ -36,8 +35,6 @@
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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u8 val);
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u8 val);
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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#define ADT7461_read_byte(address) \
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#define ADT7461_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
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#define ARA_read_byte(address) \
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#define ARA_read_byte(address) \
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <arch/coreboot_tables.h>
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#include <southbridge/amd/sb700/sb700.h>
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#include <../southbridge/amd/sb700/sb700.h>
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#include "chip.h"
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#include "chip.h"
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#define SMBUS_IO_BASE 0x6000
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#define SMBUS_IO_BASE 0x6000
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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uint64_t uma_memory_base, uma_memory_size;
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uint64_t uma_memory_base, uma_memory_size;
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void set_pcie_dereset(void);
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void set_pcie_dereset(void);
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@ -21,19 +21,15 @@
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <arch/coreboot_tables.h>
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#include <southbridge/amd/sb700/sb700.h>
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#include <../southbridge/amd/sb700/sb700.h>
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#include "chip.h"
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#include "chip.h"
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#define SMBUS_IO_BASE 0x6000
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#define SMBUS_IO_BASE 0x6000
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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uint64_t uma_memory_base, uma_memory_size;
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uint64_t uma_memory_base, uma_memory_size;
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void set_pcie_dereset(void);
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void set_pcie_dereset(void);
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <boot/tables.h>
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#include <arch/coreboot_tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <../southbridge/amd/sb600/sb600.h>
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#include <southbridge/amd/sb600/sb600.h>
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#include "chip.h"
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#include "chip.h"
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#define ADT7475_ADDRESS 0x2E
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#define ADT7475_ADDRESS 0x2E
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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u8 val);
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u8 val);
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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#define ADT7475_read_byte(address) \
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#define ADT7475_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address)
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#define ADT7475_write_byte(address, val) \
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#define ADT7475_write_byte(address, val) \
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@ -101,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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}
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}
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "lib/generic_sdram.c"
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#include "lib/generic_sdram.c"
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/* tyan does not want the default */
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/* tyan does not want the default */
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static u32 get_bus_conf_done = 0;
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static u32 get_bus_conf_done = 0;
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void get_bus_conf(void);
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void get_bus_conf(void)
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void get_bus_conf(void)
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{
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{
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u32 apicid_base;
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u32 apicid_base;
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <boot/tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <device/pci_def.h>
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#include <arch/coreboot_tables.h>
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#include <southbridge/amd/sb700/sb700.h>
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#include <../southbridge/amd/sb700/sb700.h>
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#include "chip.h"
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#include "chip.h"
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#define SMBUS_IO_BASE 0x6000
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#define SMBUS_IO_BASE 0x6000
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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uint64_t uma_memory_base, uma_memory_size;
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uint64_t uma_memory_base, uma_memory_size;
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void set_pcie_dereset(void);
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void set_pcie_dereset(void);
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@ -105,10 +105,11 @@ void soft_reset(void)
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#define K8_4RANK_DIMM_SUPPORT 1
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#define K8_4RANK_DIMM_SUPPORT 1
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "lib/generic_sdram.c"
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#include "lib/generic_sdram.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#include "southbridge/via/k8t890/k8t890_early_car.c"
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#include "southbridge/via/k8t890/k8t890_early_car.c"
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@ -126,7 +127,7 @@ unsigned int get_sbdn(unsigned bus)
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return (dev >> 15) & 0x1f;
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return (dev >> 15) & 0x1f;
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}
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}
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void sio_init(void)
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static void sio_init(void)
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{
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{
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u8 reg;
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u8 reg;
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@ -171,17 +172,17 @@ void sio_init(void)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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{
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static const uint16_t spd_addr[] = {
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static const uint16_t spd_addr[] = {
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// Node 0
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(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
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(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
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(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
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(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
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#if CONFIG_MAX_PHYSICAL_CPUS > 1
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// Node 1
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(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
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(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
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(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
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(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
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#endif
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};
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};
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unsigned bsp_apicid = 0;
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unsigned bsp_apicid = 0;
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int needs_reset = 0;
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int needs_reset = 0;
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struct sys_info *sysinfo =
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struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
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(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
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+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
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sio_init();
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sio_init();
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w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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@ -21,9 +21,8 @@
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#include <device/pci.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ids.h>
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#include <boot/tables.h>
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#include <boot/tables.h>
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#include <arch/coreboot_tables.h>
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#include "chip.h"
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#include <southbridge/via/k8t890/k8t890.h>
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#include <southbridge/via/k8t890/k8t890.h>
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#include "chip.h"
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int add_mainboard_resources(struct lb_memory *mem)
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int add_mainboard_resources(struct lb_memory *mem)
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{
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{
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@ -70,10 +70,6 @@ unsigned int get_sbdn(unsigned bus);
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#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
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#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
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#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
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static void memreset_setup(void)
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{
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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{
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}
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}
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@ -83,18 +79,20 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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return smbus_read_byte(device, address);
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return smbus_read_byte(device, address);
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}
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}
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void activate_spd_rom(const struct mem_controller *ctrl)
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static void activate_spd_rom(const struct mem_controller *ctrl)
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{
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{
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}
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}
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#define K8_4RANK_DIMM_SUPPORT 1
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#define K8_4RANK_DIMM_SUPPORT 1
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#include "southbridge/via/k8t890/k8t890_early_car.c"
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#include "southbridge/via/k8t890/k8t890_early_car.c"
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "lib/generic_sdram.c"
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#include "lib/generic_sdram.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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@ -144,34 +142,21 @@ unsigned int get_sbdn(unsigned bus)
|
||||||
return (dev >> 15) & 0x1f;
|
return (dev >> 15) & 0x1f;
|
||||||
}
|
}
|
||||||
|
|
||||||
void sio_init(void)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
|
|
||||||
|
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
{
|
|
||||||
real_main(bist, cpu_init_detectedx);
|
|
||||||
}
|
|
||||||
|
|
||||||
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
|
||||||
{
|
{
|
||||||
static const uint16_t spd_addr[] = {
|
static const uint16_t spd_addr[] = {
|
||||||
|
// Node 0
|
||||||
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
||||||
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
||||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
// Node 1
|
||||||
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
||||||
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
unsigned bsp_apicid = 0;
|
unsigned bsp_apicid = 0;
|
||||||
int needs_reset = 0;
|
int needs_reset = 0;
|
||||||
struct sys_info *sysinfo =
|
struct sys_info *sysinfo =
|
||||||
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||||
|
|
||||||
sio_init();
|
|
||||||
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
it8712f_kill_watchdog();
|
it8712f_kill_watchdog();
|
||||||
it8712f_enable_3vsbsw();
|
it8712f_enable_3vsbsw();
|
||||||
|
@ -234,7 +219,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
/* It's the time to set ctrl now. */
|
/* It's the time to set ctrl now. */
|
||||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
memreset_setup();
|
|
||||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||||
post_cache_as_ram();
|
post_cache_as_ram();
|
||||||
}
|
}
|
||||||
|
|
|
@ -86,10 +86,6 @@
|
||||||
|
|
||||||
#include "southbridge/sis/sis966/sis966_early_ctrl.c"
|
#include "southbridge/sis/sis966/sis966_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -105,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -165,12 +158,12 @@ static void sio_setup(void)
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
{
|
{
|
||||||
static const uint16_t spd_addr [] = {
|
static const uint16_t spd_addr [] = {
|
||||||
|
// Node 0
|
||||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
// Node 1
|
||||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
|
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
|
||||||
|
@ -275,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
sis_init_stage1();
|
sis_init_stage1();
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
|
|
@ -84,10 +84,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -103,12 +99,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -132,8 +125,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
@ -145,8 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
|
|
||||||
static void sio_setup(void)
|
static void sio_setup(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
unsigned value;
|
|
||||||
uint32_t dword;
|
uint32_t dword;
|
||||||
uint8_t byte;
|
uint8_t byte;
|
||||||
|
|
||||||
|
@ -166,15 +155,16 @@ static void sio_setup(void)
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
{
|
{
|
||||||
static const uint16_t spd_addr [] = {
|
static const uint16_t spd_addr [] = {
|
||||||
|
// Node 0
|
||||||
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
|
||||||
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
|
||||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
// Node 1
|
||||||
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
|
||||||
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
|
||||||
|
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||||
|
|
||||||
int needs_reset = 0;
|
int needs_reset = 0;
|
||||||
unsigned bsp_apicid = 0;
|
unsigned bsp_apicid = 0;
|
||||||
|
@ -289,8 +279,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
|
|
@ -107,16 +107,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
//#include "resourcemap.c"
|
|
||||||
|
|
||||||
#include "cpu/amd/dualcore/dualcore.c"
|
#include "cpu/amd/dualcore/dualcore.c"
|
||||||
|
|
||||||
//first node
|
//first node
|
||||||
|
@ -212,8 +207,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||||
|
|
||||||
//setup_mp_resource_map();
|
|
||||||
|
|
||||||
uart_init();
|
uart_init();
|
||||||
|
|
||||||
/* Halt if there was a built in self test failure */
|
/* Halt if there was a built in self test failure */
|
||||||
|
|
|
@ -38,7 +38,7 @@ static void print_reg(unsigned char index)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void xbus_en(void)
|
static inline void xbus_en(void)
|
||||||
{
|
{
|
||||||
/* select the XBUS function in the SIO */
|
/* select the XBUS function in the SIO */
|
||||||
outb(0x07, 0x2e);
|
outb(0x07, 0x2e);
|
||||||
|
@ -66,7 +66,7 @@ static void setup_func(unsigned char func)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void siodump(void)
|
static inline void siodump(void)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
unsigned char data;
|
unsigned char data;
|
||||||
|
@ -143,7 +143,7 @@ static void print_debug_pci_dev(unsigned dev)
|
||||||
print_debug_hex8((dev >> 8) & 7);
|
print_debug_hex8((dev >> 8) & 7);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void print_pci_devices(void)
|
static inline void print_pci_devices(void)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(0, 0, 0);
|
for(dev = PCI_DEV(0, 0, 0);
|
||||||
|
@ -161,7 +161,7 @@ static void print_pci_devices(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_pci_device(unsigned dev)
|
static inline void dump_pci_device(unsigned dev)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
print_debug_pci_dev(dev);
|
print_debug_pci_dev(dev);
|
||||||
|
@ -182,7 +182,7 @@ static void dump_pci_device(unsigned dev)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_bar14(unsigned dev)
|
static inline void dump_bar14(unsigned dev)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
unsigned long bar;
|
unsigned long bar;
|
||||||
|
@ -227,70 +227,7 @@ static void dump_pci_devices(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if 0
|
static inline void dump_spd_registers(void)
|
||||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
print_debug("\n");
|
|
||||||
for(i = 0; i < 4; i++) {
|
|
||||||
unsigned device;
|
|
||||||
device = ctrl->channel0[i];
|
|
||||||
if (device) {
|
|
||||||
int j;
|
|
||||||
print_debug("dimm: ");
|
|
||||||
print_debug_hex8(i);
|
|
||||||
print_debug(".0: ");
|
|
||||||
print_debug_hex8(device);
|
|
||||||
for(j = 0; j < 256; j++) {
|
|
||||||
int status;
|
|
||||||
unsigned char byte;
|
|
||||||
if ((j & 0xf) == 0) {
|
|
||||||
print_debug("\n");
|
|
||||||
print_debug_hex8(j);
|
|
||||||
print_debug(": ");
|
|
||||||
}
|
|
||||||
status = smbus_read_byte(device, j);
|
|
||||||
if (status < 0) {
|
|
||||||
print_debug("bad device\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
byte = status & 0xff;
|
|
||||||
print_debug_hex8(byte);
|
|
||||||
print_debug_char(' ');
|
|
||||||
}
|
|
||||||
print_debug("\n");
|
|
||||||
}
|
|
||||||
device = ctrl->channel1[i];
|
|
||||||
if (device) {
|
|
||||||
int j;
|
|
||||||
print_debug("dimm: ");
|
|
||||||
print_debug_hex8(i);
|
|
||||||
print_debug(".1: ");
|
|
||||||
print_debug_hex8(device);
|
|
||||||
for(j = 0; j < 256; j++) {
|
|
||||||
int status;
|
|
||||||
unsigned char byte;
|
|
||||||
if ((j & 0xf) == 0) {
|
|
||||||
print_debug("\n");
|
|
||||||
print_debug_hex8(j);
|
|
||||||
print_debug(": ");
|
|
||||||
}
|
|
||||||
status = smbus_read_byte(device, j);
|
|
||||||
if (status < 0) {
|
|
||||||
print_debug("bad device\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
byte = status & 0xff;
|
|
||||||
print_debug_hex8(byte);
|
|
||||||
print_debug_char(' ');
|
|
||||||
}
|
|
||||||
print_debug("\n");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void dump_spd_registers(void)
|
|
||||||
{
|
{
|
||||||
unsigned device;
|
unsigned device;
|
||||||
device = SMBUS_MEM_DEVICE_START;
|
device = SMBUS_MEM_DEVICE_START;
|
||||||
|
@ -322,7 +259,7 @@ void dump_spd_registers(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void dump_ipmi_registers(void)
|
static inline void dump_ipmi_registers(void)
|
||||||
{
|
{
|
||||||
unsigned device;
|
unsigned device;
|
||||||
device = 0x42;
|
device = 0x42;
|
||||||
|
|
|
@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8.h"
|
#include "northbridge/amd/amdk8/amdk8.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit.c"
|
#include "northbridge/amd/amdk8/raminit.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
#include "lib/ramtest.c"
|
#include "lib/ramtest.c"
|
||||||
|
|
||||||
|
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#define DIMM6 0x56
|
#define DIMM6 0x56
|
||||||
#define DIMM7 0x57
|
#define DIMM7 0x57
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
|
|
@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8.h"
|
#include "northbridge/amd/amdk8/amdk8.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit.c"
|
#include "northbridge/amd/amdk8/raminit.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
#include "lib/ramtest.c"
|
#include "lib/ramtest.c"
|
||||||
|
|
||||||
|
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#define DIMM6 0x56
|
#define DIMM6 0x56
|
||||||
#define DIMM7 0x57
|
#define DIMM7 0x57
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
|
|
@ -90,12 +90,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8.h"
|
#include "northbridge/amd/amdk8/amdk8.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit.c"
|
#include "northbridge/amd/amdk8/raminit.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
#include "lib/ramtest.c"
|
#include "lib/ramtest.c"
|
||||||
|
|
||||||
|
@ -113,7 +110,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#define DIMM6 0x56
|
#define DIMM6 0x56
|
||||||
#define DIMM7 0x57
|
#define DIMM7 0x57
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
|
|
@ -21,8 +21,7 @@
|
||||||
#include <device/device.h>
|
#include <device/device.h>
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <boot/coreboot_tables.h>
|
#include <boot/tables.h>
|
||||||
#include <arch/coreboot_tables.h>
|
|
||||||
#include <cpu/x86/msr.h>
|
#include <cpu/x86/msr.h>
|
||||||
#include <cpu/amd/mtrr.h>
|
#include <cpu/amd/mtrr.h>
|
||||||
#include <device/pci_def.h>
|
#include <device/pci_def.h>
|
||||||
|
@ -36,8 +35,6 @@
|
||||||
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
||||||
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
||||||
u8 val);
|
u8 val);
|
||||||
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
|
|
||||||
uint64_t start, uint64_t size);
|
|
||||||
#define ADT7461_read_byte(address) \
|
#define ADT7461_read_byte(address) \
|
||||||
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
||||||
#define ARA_read_byte(address) \
|
#define ARA_read_byte(address) \
|
||||||
|
|
|
@ -83,7 +83,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void) {}
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl) {}
|
static void memreset(int controllers, const struct mem_controller *ctrl) {}
|
||||||
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
|
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
|
||||||
|
|
||||||
|
@ -93,10 +92,11 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
#include "cpu/amd/dualcore/dualcore.c"
|
#include "cpu/amd/dualcore/dualcore.c"
|
||||||
|
|
||||||
|
@ -144,16 +144,17 @@ static void sio_setup(void)
|
||||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
{
|
{
|
||||||
static const uint16_t spd_addr[] = {
|
static const uint16_t spd_addr[] = {
|
||||||
|
// Node 0
|
||||||
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
||||||
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
||||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
// Node 1
|
||||||
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
||||||
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
||||||
#endif
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct sys_info *sysinfo =
|
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
|
||||||
(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||||
|
|
||||||
int needs_reset = 0;
|
int needs_reset = 0;
|
||||||
unsigned bsp_apicid = 0;
|
unsigned bsp_apicid = 0;
|
||||||
|
|
||||||
|
@ -252,8 +253,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
/* Do we need apci timer, tsc...., only debug need it for better output */
|
/* Do we need apci timer, tsc...., only debug need it for better output */
|
||||||
/* All AP stopped? */
|
/* All AP stopped? */
|
||||||
// init_timer(); /* Need to use TMICT to synconize FID/VID. */
|
// init_timer(); /* Need to use TMICT to synconize FID/VID. */
|
||||||
|
|
|
@ -71,9 +71,6 @@
|
||||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
|
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
|
||||||
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
|
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
|
||||||
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
|
#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
|
@ -104,12 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
/* msi does not want the default */
|
/* msi does not want the default */
|
||||||
|
@ -129,7 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#define DIMM6 0x56
|
#define DIMM6 0x56
|
||||||
#define DIMM7 0x57
|
#define DIMM7 0x57
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
@ -144,12 +137,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
//first node
|
//first node
|
||||||
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
|
RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
|
||||||
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
|
RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
|
||||||
#if CONFIG_MAX_PHYSICAL_CPUS > 1
|
|
||||||
//second node
|
//second node
|
||||||
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
|
RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
|
||||||
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
|
RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
|
||||||
#endif
|
|
||||||
|
|
||||||
};
|
};
|
||||||
|
|
||||||
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
|
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
|
||||||
|
@ -278,8 +268,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
|
|
@ -68,9 +68,6 @@
|
||||||
|
|
||||||
#include <device/pci_ids.h>
|
#include <device/pci_ids.h>
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
|
@ -103,9 +100,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
//#define K8_4RANK_DIMM_SUPPORT 1
|
//#define K8_4RANK_DIMM_SUPPORT 1
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
/* msi does not want the default */
|
/* msi does not want the default */
|
||||||
|
@ -228,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||||
|
|
||||||
post_cache_as_ram();
|
post_cache_as_ram();
|
||||||
|
|
|
@ -92,11 +92,9 @@ static unsigned get_hcid(unsigned i)
|
||||||
|
|
||||||
void get_bus_conf(void)
|
void get_bus_conf(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
unsigned apicid_base;
|
unsigned apicid_base;
|
||||||
struct mb_sysconf_t *m;
|
struct mb_sysconf_t *m;
|
||||||
|
|
||||||
device_t dev;
|
|
||||||
int i, j;
|
int i, j;
|
||||||
|
|
||||||
if (get_bus_conf_done)
|
if (get_bus_conf_done)
|
||||||
|
@ -160,5 +158,4 @@ void get_bus_conf(void)
|
||||||
#endif
|
#endif
|
||||||
m->apicid_mcp55 = apicid_base+0;
|
m->apicid_mcp55 = apicid_base+0;
|
||||||
m->apicid_mcp55b = apicid_base+1;
|
m->apicid_mcp55b = apicid_base+1;
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -83,10 +83,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -274,8 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
|
|
@ -69,7 +69,7 @@ static void init_dcon(void) {
|
||||||
write_bit(rev > 0 ? 1 : 0);
|
write_bit(rev > 0 ? 1 : 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
static void
|
||||||
init_cafe_irq(void){
|
init_cafe_irq(void){
|
||||||
const unsigned char slots_cafe[4] = {11, 0, 0, 0};
|
const unsigned char slots_cafe[4] = {11, 0, 0, 0};
|
||||||
|
|
||||||
|
|
|
@ -7,6 +7,7 @@
|
||||||
#include <cpu/amd/multicore.h>
|
#include <cpu/amd/multicore.h>
|
||||||
#endif
|
#endif
|
||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
|
#include <cpu/amd/amdk8_sysconf.h>
|
||||||
|
|
||||||
|
|
||||||
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
|
||||||
|
|
|
@ -9,6 +9,7 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <arch/pirq_routing.h>
|
#include <arch/pirq_routing.h>
|
||||||
|
#include <cpu/amd/amdk8_sysconf.h>
|
||||||
|
|
||||||
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
|
||||||
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
|
||||||
|
|
|
@ -3,6 +3,7 @@
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
#include <cpu/amd/amdk8_sysconf.h>
|
||||||
|
|
||||||
extern unsigned char bus_isa;
|
extern unsigned char bus_isa;
|
||||||
extern unsigned char bus_ck804_0; //1
|
extern unsigned char bus_ck804_0; //1
|
||||||
|
@ -32,8 +33,6 @@ extern unsigned hcdn[];
|
||||||
extern unsigned sbdn3;
|
extern unsigned sbdn3;
|
||||||
extern unsigned sbdnb;
|
extern unsigned sbdnb;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
static void *smp_write_config_table(void *v)
|
static void *smp_write_config_table(void *v)
|
||||||
{
|
{
|
||||||
static const char sig[4] = "PCMP";
|
static const char sig[4] = "PCMP";
|
||||||
|
|
|
@ -77,10 +77,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -154,12 +150,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -175,8 +168,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
@ -340,8 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
enable_smbus(); /* enable in sio_setup */
|
enable_smbus(); /* enable in sio_setup */
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
|
|
@ -80,10 +80,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -99,12 +95,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -120,8 +113,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
@ -263,8 +254,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
// enable_smbus(); /* enable in sio_setup */
|
// enable_smbus(); /* enable in sio_setup */
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
@ -272,6 +261,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||||
|
|
||||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -21,8 +21,7 @@
|
||||||
#include <device/device.h>
|
#include <device/device.h>
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <boot/coreboot_tables.h>
|
#include <boot/tables.h>
|
||||||
#include <arch/coreboot_tables.h>
|
|
||||||
#include <cpu/x86/msr.h>
|
#include <cpu/x86/msr.h>
|
||||||
#include <cpu/amd/mtrr.h>
|
#include <cpu/amd/mtrr.h>
|
||||||
#include <device/pci_def.h>
|
#include <device/pci_def.h>
|
||||||
|
@ -179,7 +178,7 @@ static void set_thermal_config(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Mainboard specific GPIO setup. */
|
/* Mainboard specific GPIO setup. */
|
||||||
void mb_gpio_init(u16 *iobase)
|
static void mb_gpio_init(u16 *iobase)
|
||||||
{
|
{
|
||||||
/* Init Super I/O GPIOs. */
|
/* Init Super I/O GPIOs. */
|
||||||
it8712f_enter_conf();
|
it8712f_enter_conf();
|
||||||
|
@ -193,7 +192,7 @@ void mb_gpio_init(u16 *iobase)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The LCD's panel id seletion. */
|
/* The LCD's panel id seletion. */
|
||||||
void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
|
static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
|
||||||
{
|
{
|
||||||
switch (num_id) {
|
switch (num_id) {
|
||||||
case 0x1:
|
case 0x1:
|
||||||
|
@ -226,9 +225,6 @@ void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id)
|
||||||
*************************************************/
|
*************************************************/
|
||||||
static void tim5690_enable(device_t dev)
|
static void tim5690_enable(device_t dev)
|
||||||
{
|
{
|
||||||
struct mainboard_config *mainboard =
|
|
||||||
(struct mainboard_config *)dev->chip_info;
|
|
||||||
|
|
||||||
rs690_vbios_regs vbios_regs;
|
rs690_vbios_regs vbios_regs;
|
||||||
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
|
u16 gpio_base = IT8712F_SIMPLE_IO_BASE;
|
||||||
u8 port2;
|
u8 port2;
|
||||||
|
@ -240,6 +236,7 @@ static void tim5690_enable(device_t dev)
|
||||||
/* The LCD's panel id seletion by switch. */
|
/* The LCD's panel id seletion by switch. */
|
||||||
port2 = inb(gpio_base+1);
|
port2 = inb(gpio_base+1);
|
||||||
lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
|
lcd_panel_id(&vbios_regs, ((~port2) & 0xf));
|
||||||
|
|
||||||
/* No support TV */
|
/* No support TV */
|
||||||
vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
|
vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
|
||||||
vgabios_init(&vbios_regs);
|
vgabios_init(&vbios_regs);
|
||||||
|
|
|
@ -36,6 +36,7 @@ static void vbios_fun_init(rs690_vbios_regs *vbios_regs)
|
||||||
vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
|
vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id;
|
||||||
vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
|
vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* BIOS int15 function */
|
/* BIOS int15 function */
|
||||||
int tim5690_int15_handler(struct eregs *regs)
|
int tim5690_int15_handler(struct eregs *regs)
|
||||||
{
|
{
|
||||||
|
|
|
@ -21,12 +21,11 @@
|
||||||
#include <device/device.h>
|
#include <device/device.h>
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <arch/io.h>
|
#include <arch/io.h>
|
||||||
#include <boot/coreboot_tables.h>
|
#include <boot/tables.h>
|
||||||
#include <arch/coreboot_tables.h>
|
|
||||||
#include <cpu/x86/msr.h>
|
#include <cpu/x86/msr.h>
|
||||||
#include <cpu/amd/mtrr.h>
|
#include <cpu/amd/mtrr.h>
|
||||||
#include <device/pci_def.h>
|
#include <device/pci_def.h>
|
||||||
#include <../southbridge/amd/sb600/sb600.h>
|
#include <southbridge/amd/sb600/sb600.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
|
||||||
#define ADT7461_ADDRESS 0x4C
|
#define ADT7461_ADDRESS 0x4C
|
||||||
|
@ -36,8 +35,6 @@
|
||||||
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
|
||||||
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
|
||||||
u8 val);
|
u8 val);
|
||||||
extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
|
|
||||||
uint64_t start, uint64_t size);
|
|
||||||
#define ADT7461_read_byte(address) \
|
#define ADT7461_read_byte(address) \
|
||||||
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
|
||||||
#define ARA_read_byte(address) \
|
#define ARA_read_byte(address) \
|
||||||
|
|
|
@ -15,7 +15,6 @@
|
||||||
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
|
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
|
||||||
#include "northbridge/intel/e7501/raminit.h"
|
#include "northbridge/intel/e7501/raminit.h"
|
||||||
|
|
||||||
#include "cpu/x86/lapic/boot_cpu.c"
|
|
||||||
#include "northbridge/intel/e7501/debug.c"
|
#include "northbridge/intel/e7501/debug.c"
|
||||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||||
|
|
||||||
|
|
|
@ -83,10 +83,6 @@
|
||||||
|
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
|
||||||
|
|
||||||
static void memreset_setup(void)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
@ -102,12 +98,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
}
|
}
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/amdk8_f.h"
|
#include "northbridge/amd/amdk8/amdk8_f.h"
|
||||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
|
||||||
|
|
||||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||||
|
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||||
#include "northbridge/amd/amdk8/raminit_f.c"
|
#include "northbridge/amd/amdk8/raminit_f.c"
|
||||||
|
|
||||||
#include "lib/generic_sdram.c"
|
#include "lib/generic_sdram.c"
|
||||||
|
|
||||||
#include "resourcemap.c"
|
#include "resourcemap.c"
|
||||||
|
@ -130,8 +123,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
|
||||||
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "cpu/amd/car/post_cache_as_ram.c"
|
#include "cpu/amd/car/post_cache_as_ram.c"
|
||||||
|
|
||||||
#include "cpu/amd/model_fxx/init_cpus.c"
|
#include "cpu/amd/model_fxx/init_cpus.c"
|
||||||
|
@ -271,8 +262,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
|
|
||||||
enable_smbus();
|
enable_smbus();
|
||||||
|
|
||||||
memreset_setup();
|
|
||||||
|
|
||||||
//do we need apci timer, tsc...., only debug need it for better output
|
//do we need apci timer, tsc...., only debug need it for better output
|
||||||
/* all ap stopped? */
|
/* all ap stopped? */
|
||||||
// init_timer(); // Need to use TMICT to synconize FID/VID
|
// init_timer(); // Need to use TMICT to synconize FID/VID
|
||||||
|
@ -280,6 +269,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||||
|
|
||||||
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -19,5 +19,8 @@
|
||||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
##
|
##
|
||||||
|
|
||||||
obj-y += wakeup.o
|
# This code is unused and should be replaced by the generic resume code
|
||||||
|
# completely. If anyone works on wakeup for this chipset/board, delete
|
||||||
|
# wakeup.c when you are done.
|
||||||
|
# obj-y += wakeup.o
|
||||||
|
|
||||||
|
|
|
@ -19,6 +19,10 @@
|
||||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/* FIXME This code should be dropped and instead the generic resume code
|
||||||
|
* should be used.
|
||||||
|
*/
|
||||||
|
|
||||||
/* Parts of this code is taken from reboot.c from Linux. */
|
/* Parts of this code is taken from reboot.c from Linux. */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -96,19 +100,6 @@ static unsigned char jump_to_wakeup[] = {
|
||||||
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
|
0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
|
||||||
* Switch to real mode and then execute the code
|
|
||||||
* specified by the code and length parameters.
|
|
||||||
* We assume that length will aways be less that 100!
|
|
||||||
*/
|
|
||||||
static unsigned char show31[6] = {
|
|
||||||
0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned char show32[6] = {
|
|
||||||
0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */
|
|
||||||
};
|
|
||||||
|
|
||||||
void acpi_jump_wake(u32 vector)
|
void acpi_jump_wake(u32 vector)
|
||||||
{
|
{
|
||||||
u32 dwEip;
|
u32 dwEip;
|
||||||
|
@ -337,8 +328,6 @@ void acpi_jump_wake(u32 vector)
|
||||||
* Enable A20 gate (return -1 on failure)
|
* Enable A20 gate (return -1 on failure)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
// #include "boot.h"
|
|
||||||
|
|
||||||
#define MAX_8042_LOOPS 100000
|
#define MAX_8042_LOOPS 100000
|
||||||
|
|
||||||
static int empty_8042(void)
|
static int empty_8042(void)
|
||||||
|
@ -375,13 +364,9 @@ static int a20_test(int loops)
|
||||||
int ok = 0;
|
int ok = 0;
|
||||||
int saved, ctr;
|
int saved, ctr;
|
||||||
|
|
||||||
// set_fs(0x0000);
|
|
||||||
// set_gs(0xffff);
|
|
||||||
|
|
||||||
saved = ctr = *((u32 *) A20_TEST_ADDR);
|
saved = ctr = *((u32 *) A20_TEST_ADDR);
|
||||||
|
|
||||||
while (loops--) {
|
while (loops--) {
|
||||||
//wrfs32(++ctr, A20_TEST_ADDR);
|
|
||||||
|
|
||||||
*((u32 *) A20_TEST_ADDR) = ++ctr;
|
*((u32 *) A20_TEST_ADDR) = ++ctr;
|
||||||
|
|
||||||
|
|
|
@ -23,8 +23,8 @@
|
||||||
#include <device/pci.h>
|
#include <device/pci.h>
|
||||||
#include <device/pci_ids.h>
|
#include <device/pci_ids.h>
|
||||||
#include <boot/tables.h>
|
#include <boot/tables.h>
|
||||||
|
#include <southbridge/via/vt8237r/vt8237r.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "../../../southbridge/via/vt8237r/vt8237r.h"
|
|
||||||
|
|
||||||
int add_mainboard_resources(struct lb_memory *mem)
|
int add_mainboard_resources(struct lb_memory *mem)
|
||||||
{
|
{
|
||||||
|
|
|
@ -718,12 +718,14 @@ static int is_dual_channel(const struct mem_controller *ctrl)
|
||||||
|
|
||||||
static int is_opteron(const struct mem_controller *ctrl)
|
static int is_opteron(const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
/* Test to see if I am an Opteron.
|
/* Test to see if I am an Opteron. M2 and S1G1 support dual
|
||||||
* FIXME Testing dual channel capability is correct for now
|
* channel, too, but only support unbuffered DIMMs so we need a
|
||||||
* but a better test is probably required.
|
* better test for Opterons.
|
||||||
* m2 and s1g1 support dual channel too. but only support unbuffered dimm
|
* However, all code uses is_opteron() to find out whether to
|
||||||
|
* use dual channel, so if we really check for opteron here, we
|
||||||
|
* need to fix up all code using this function, too.
|
||||||
*/
|
*/
|
||||||
#warning "FIXME implement a better test for opterons"
|
|
||||||
uint32_t nbcap;
|
uint32_t nbcap;
|
||||||
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
|
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
|
||||||
return !!(nbcap & NBCAP_128Bit);
|
return !!(nbcap & NBCAP_128Bit);
|
||||||
|
|
|
@ -13,7 +13,7 @@ static void print_debug_pci_dev(unsigned dev)
|
||||||
print_debug_hex8((dev >> 8) & 7);
|
print_debug_hex8((dev >> 8) & 7);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void print_pci_devices(void)
|
static inline void print_pci_devices(void)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(0, 0, 0);
|
for(dev = PCI_DEV(0, 0, 0);
|
||||||
|
@ -58,7 +58,7 @@ static void dump_pci_device(unsigned dev)
|
||||||
print_debug("\n");
|
print_debug("\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_pci_devices(void)
|
static inline void dump_pci_devices(void)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(0, 0, 0);
|
for(dev = PCI_DEV(0, 0, 0);
|
||||||
|
@ -75,7 +75,7 @@ static void dump_pci_devices(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_pci_devices_on_bus(unsigned busn)
|
static inline void dump_pci_devices_on_bus(unsigned busn)
|
||||||
{
|
{
|
||||||
device_t dev;
|
device_t dev;
|
||||||
for(dev = PCI_DEV(busn, 0, 0);
|
for(dev = PCI_DEV(busn, 0, 0);
|
||||||
|
@ -92,7 +92,7 @@ static void dump_pci_devices_on_bus(unsigned busn)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_spd_registers(const struct mem_controller *ctrl)
|
static inline void dump_spd_registers(const struct mem_controller *ctrl)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
print_debug("\n");
|
print_debug("\n");
|
||||||
|
@ -174,7 +174,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
static void dump_smbus_registers(void)
|
static inline void dump_smbus_registers(void)
|
||||||
{
|
{
|
||||||
unsigned device;
|
unsigned device;
|
||||||
print_debug("\n");
|
print_debug("\n");
|
||||||
|
@ -215,7 +215,7 @@ static void dump_smbus_registers(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_io_resources(unsigned port)
|
static inline void dump_io_resources(unsigned port)
|
||||||
{
|
{
|
||||||
|
|
||||||
int i;
|
int i;
|
||||||
|
@ -249,7 +249,7 @@ static void dump_io_resources(unsigned port)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void dump_mem(unsigned start, unsigned end)
|
static inline void dump_mem(unsigned start, unsigned end)
|
||||||
{
|
{
|
||||||
unsigned i;
|
unsigned i;
|
||||||
print_debug("dump_mem:");
|
print_debug("dump_mem:");
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -15,5 +15,8 @@ struct mem_controller {
|
||||||
uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
|
uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#ifndef __ROMCC__
|
||||||
|
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* RAMINIT_H */
|
#endif /* RAMINIT_H */
|
||||||
|
|
|
@ -29,7 +29,6 @@
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <bitops.h>
|
#include <bitops.h>
|
||||||
#include <boot/tables.h>
|
#include <boot/tables.h>
|
||||||
#include <arch/coreboot_tables.h>
|
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "i82830.h"
|
#include "i82830.h"
|
||||||
|
|
||||||
|
|
|
@ -31,7 +31,6 @@
|
||||||
#include <boot/tables.h>
|
#include <boot/tables.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "i945.h"
|
#include "i945.h"
|
||||||
#include <arch/coreboot_tables.h>
|
|
||||||
|
|
||||||
static int get_pcie_bar(u32 *base, u32 *len)
|
static int get_pcie_bar(u32 *base, u32 *len)
|
||||||
{
|
{
|
||||||
|
|
|
@ -29,6 +29,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
|
||||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef UNUSED_CODE
|
||||||
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
|
static void smbus_write_byte(unsigned device, unsigned address, unsigned char val)
|
||||||
{
|
{
|
||||||
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
|
if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) {
|
||||||
|
@ -126,4 +127,4 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
|
||||||
print_debug("SMBUS Block complete\n");
|
print_debug("SMBUS Block complete\n");
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
|
@ -7,18 +7,9 @@
|
||||||
#include <pc80/i8259.h>
|
#include <pc80/i8259.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
|
||||||
/*
|
|
||||||
* Base VT8235.
|
|
||||||
*/
|
|
||||||
|
|
||||||
void hard_reset(void)
|
|
||||||
{
|
|
||||||
printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
static void keyboard_on(struct device *dev)
|
static void keyboard_on(struct device *dev)
|
||||||
{
|
{
|
||||||
unsigned char regval;
|
u8 regval;
|
||||||
|
|
||||||
regval = pci_read_config8(dev, 0x51);
|
regval = pci_read_config8(dev, 0x51);
|
||||||
regval |= 0x05;
|
regval |= 0x05;
|
||||||
|
@ -28,6 +19,7 @@ static void keyboard_on(struct device *dev)
|
||||||
pc_keyboard_init(0);
|
pc_keyboard_init(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef UNUSED_CODE
|
||||||
void dump_south(device_t dev0)
|
void dump_south(device_t dev0)
|
||||||
{
|
{
|
||||||
int i,j;
|
int i,j;
|
||||||
|
@ -43,33 +35,37 @@ void dump_south(device_t dev0)
|
||||||
|
|
||||||
void set_led(void)
|
void set_led(void)
|
||||||
{
|
{
|
||||||
// set power led to steady now that lxbios has virtually done its job
|
// set power led to steady now that coreboot has virtually done its job
|
||||||
device_t dev;
|
device_t dev;
|
||||||
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
|
dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
|
||||||
pci_write_config8(dev, 0x94, 0xb0);
|
pci_write_config8(dev, 0x94, 0xb0);
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
static void vt8235_enable(struct device *dev)
|
static void vt8235_enable(struct device *dev)
|
||||||
{
|
{
|
||||||
unsigned char regval;
|
u8 regval;
|
||||||
unsigned short vendor,model;
|
u16 vendor,model;
|
||||||
|
|
||||||
vendor = pci_read_config16(dev,0);
|
vendor = pci_read_config16(dev,0);
|
||||||
model = pci_read_config16(dev,0x2);
|
model = pci_read_config16(dev,0x2);
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
|
printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
|
||||||
|
|
||||||
/* if this is not the southbridge itself just return */
|
/* If this is not the southbridge itself just return.
|
||||||
/* this is necessary because USB devices are slot 10, whereas this device is slot 11
|
* This is necessary because USB devices are slot 10, whereas this
|
||||||
therefore usb devices get called first during the bus scan */
|
* device is slot 11 therefore usb devices get called first during
|
||||||
|
* the bus scan. We don't want to wait until we could do dev->init
|
||||||
|
* because that's too late.
|
||||||
|
*/
|
||||||
|
|
||||||
if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
|
if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "Initialising Devices\n");
|
printk(BIOS_DEBUG, "Initialising Devices\n");
|
||||||
|
|
||||||
setup_i8259(); // make sure interupt controller is configured before keyboard init
|
/* make sure interupt controller is configured before keyboard init */
|
||||||
|
setup_i8259();
|
||||||
|
|
||||||
/* enable RTC and ethernet */
|
/* enable RTC and ethernet */
|
||||||
regval = pci_read_config8(dev, 0x51);
|
regval = pci_read_config8(dev, 0x51);
|
||||||
|
@ -79,7 +75,9 @@ static void vt8235_enable(struct device *dev)
|
||||||
/* turn on keyboard */
|
/* turn on keyboard */
|
||||||
keyboard_on(dev);
|
keyboard_on(dev);
|
||||||
|
|
||||||
/* enable USB 1.1 & USB 2.0 -redundant really since we've already been there - see note above*/
|
/* enable USB 1.1 & USB 2.0 - redundant really since we've
|
||||||
|
* already been there - see note above
|
||||||
|
*/
|
||||||
regval = pci_read_config8(dev, 0x50);
|
regval = pci_read_config8(dev, 0x50);
|
||||||
regval &= ~(0x36);
|
regval &= ~(0x36);
|
||||||
pci_write_config8(dev, 0x50, regval);
|
pci_write_config8(dev, 0x50, regval);
|
||||||
|
|
Loading…
Reference in New Issue