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src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource 

Ideally don't need to mark the entire top_of_ram till TOLUD range (used
for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as
cacheable for OS usage as coreboot already done with mpinit w/ smm
relocation early.

TEST=Able to build and boot ICL, TGL RVP.

Without this CL :

PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a

With this CL :

PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index 9

No changes observed with MTRRs snapshot.

Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2020-07-29 11:01:26 +05:30
parent e58c6f5dfa
commit 239272e43d
1 changed files with 6 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
src/soc/intel/common/block/systemagent/systemagent.c
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@ -158,8 +158,7 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
* These are the host memory ranges that should be added:
* - 0 -> 0xa0000: cacheable
* - 0xc0000 -> top_of_ram : cacheable
* - top_of_ram -> BGSM: cacheable with standard MTRRs and reserved
* - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved
* - top_of_ram -> TOLUD: not cacheable with standard MTRRs and reserved
* - 4GiB -> TOUUD: cacheable
*
* The default SMRAM space is reserved so that the range doesn't
@ -173,9 +172,10 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
* is not omitted the mtrr code will setup the area as cacheable
* causing VGA access to not work.
*
* The TSEG region is mapped as cacheable so that one can perform
* SMRAM relocation faster. Once the SMRR is enabled the SMRR takes
* precedence over the existing MTRRs covering this region.
* Don't need to mark the entire top_of_ram till TOLUD range (used
* for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as
* cacheable for OS usage as coreboot already done with mpinit w/ smm
* relocation early.
*
* It should be noted that cacheable entry types need to be added in
* order. The reason is that the current MTRR code assumes this and
@ -206,13 +206,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
sa_get_mem_map(dev, &sa_map_values[0]);
/* top_of_ram -> BGSM */
/* top_of_ram -> TOLUD */
base_k = top_of_ram;
size_k = sa_map_values[SA_BGSM_REG] - base_k;
reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB);
/* BGSM -> TOLUD */
base_k = sa_map_values[SA_BGSM_REG];
size_k = sa_map_values[SA_TOLUD_REG] - base_k;
mmio_resource(dev, index++, base_k / KiB, size_k / KiB);