mb/intel/tglrvp: Enable ISH driver and register firmware name
BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3, then copied ISH firmware to host file system /lib/firmware/intel/tglrvp_ish.bin check "dmesg |grep ish", it shows: ish-loader: ISH firmware intel/tglrvp_ish.bin loaded cros_ec_ishtp: Chrome EC device registered Those means shim loader in coreboot has loaded ISH firmware, and firmware is running successfully. Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I1ee8050aef6ec0828f16ef2695b5347278caa820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39481 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
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select GENERATE_SMBIOS_TABLES
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select SOC_INTEL_TIGERLAKE
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select INTEL_LPSS_UART_FOR_CONSOLE
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select DRIVERS_INTEL_ISH
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config CHROMEOS
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bool
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@ -133,7 +133,12 @@ chip soc/intel/tigerlake
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device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
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device pci 10.6 off end # THC0 0xA0D0
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device pci 10.7 off end # THC1 0xA0D1
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device pci 12.0 off end # SensorHUB 0xA0FC
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device pci 12.0 on # SensorHUB 0xA0FC
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chip drivers/intel/ish
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register "firmware_name" = ""tglrvp_ish.bin""
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device generic 0 on end
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end
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end
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device pci 12.6 off end # GSPI2 0x34FB
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device pci 13.0 off end # GSPI3 0xA0FD
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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@ -129,7 +129,12 @@ chip soc/intel/tigerlake
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device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7
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device pci 10.6 off end # THC0 0xA0D0
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device pci 10.7 off end # THC1 0xA0D1
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device pci 12.0 off end # SensorHUB 0xA0FC
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device pci 12.0 on # SensorHUB 0xA0FC
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chip drivers/intel/ish
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register "firmware_name" = ""tglrvp_ish.bin""
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device generic 0 on end
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end
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end
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device pci 12.6 off end # GSPI2 0x34FB
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device pci 13.0 off end # GSPI3 0xA0FD
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device pci 14.0 on end # USB3.1 xHCI 0xA0ED
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