ACPI GNVS: Replace uses of smm_get_gnvs()

Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Documentation/mainboard_io_trap_handler_sample.c

@@ -20,7 +20,7 @@ int mainboard_io_trap_handler(int smif)
        switch (smif) {
        case 0x99:
                printk(BIOS_DEBUG, "Sample\n");
-               smm_get_gnvs()->smif = 0;
+               gnvs->smif = 0;
                break;
        default:
                return 0;
@@ -32,6 +32,6 @@ int mainboard_io_trap_handler(int smif)
         * For now, we force the return value to 0 and log all traps to
         * see what's going on.
         */
-       //smm_get_gnvs()->smif = 0;
+       //gnvs->smif = 0;
        return 1;
 }

src/cpu/x86/smm/smm_module_handler.c

@@ -91,6 +91,8 @@ static void smi_restore_pci_address(void)
 
 static const struct smm_runtime *smm_runtime;
 
+struct global_nvs *gnvs;
+
 void *smm_get_save_state(int cpu)
 {
 	char *base;

src/include/cpu/x86/smm.h

@@ -86,7 +86,9 @@ struct smm_module_params {
 typedef asmlinkage void (*smm_handler_t)(void *);
 
 /* SMM Runtime helpers. */
-struct global_nvs *smm_get_gnvs(void);
+#if ENV_SMM
+extern struct global_nvs *gnvs;
+#endif
 
 /* Entry point for SMM modules. */
 asmlinkage void smm_handler_start(void *params);

src/mainboard/getac/p470/smihandler.c

@@ -11,11 +11,6 @@
 
 #define MAX_LCD_BRIGHTNESS 0xd8
 
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
- */
-extern struct global_nvs *gnvs;
-
 int mainboard_io_trap_handler(int smif)
 {
 	u8 reg8;

src/mainboard/google/auron/smihandler.c

@@ -65,7 +65,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0) {
+		if (gnvs->s3u0 == 0) {
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
 			google_chromeec_set_usb_charge_mode(
@@ -78,7 +78,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 		break;
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0) {
+		if (gnvs->s5u0 == 0) {
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
 			google_chromeec_set_usb_charge_mode(

src/mainboard/google/butterfly/mainboard_smi.c

@@ -23,7 +23,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
 
 	/* Tell the EC to Enable USB power for S3 if requested */
-	if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0)
+	if (gnvs->s3u0 != 0 || gnvs->s3u1 != 0)
 		ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB);
 
 	/* Disable wake on USB, LAN & RTC */

src/mainboard/google/cyan/smihandler.c

@@ -24,7 +24,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;
@@ -86,10 +86,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (gnvs->s3u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
+		if (gnvs->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 
@@ -99,10 +99,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 		enable_gpe(WAKE_GPIO_EN);
 		break;
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (gnvs->s5u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
+		if (gnvs->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 

src/mainboard/google/glados/smihandler.c

@@ -18,7 +18,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;

src/mainboard/google/jecht/smihandler.c

@@ -15,7 +15,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;

src/mainboard/google/link/mainboard_smi.c

@@ -49,18 +49,18 @@ void mainboard_smi_sleep(u8 slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (gnvs->s3u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
+		if (gnvs->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 		break;
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (gnvs->s5u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
+		if (gnvs->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 		break;

src/mainboard/google/parrot/smihandler.c

@@ -62,7 +62,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 
 
 	/* Tell the EC to Disable USB power */
-	if (smm_get_gnvs()->s3u0 == 0 && smm_get_gnvs()->s3u1 == 0) {
+	if (gnvs->s3u0 == 0 && gnvs->s3u1 == 0) {
 		ec_kbc_write_cmd(0x45);
 		ec_kbc_write_ib(0xF2);
 	}

src/mainboard/google/rambi/mainboard_smi.c

@@ -55,10 +55,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (gnvs->s3u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
+		if (gnvs->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 
@@ -68,10 +68,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 		enable_gpe(WAKE_GPIO_EN);
 		break;
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (gnvs->s5u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
+		if (gnvs->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 

src/mainboard/google/slippy/smihandler.c

@@ -59,10 +59,10 @@ void mainboard_smi_sleep(u8 slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (gnvs->s3u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
+		if (gnvs->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 
@@ -77,10 +77,10 @@ void mainboard_smi_sleep(u8 slp_typ)
 		break;
 	case ACPI_S4:
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (gnvs->s5u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
+		if (gnvs->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 

src/mainboard/google/stout/mainboard_smi.c

@@ -49,7 +49,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 	 *             charge smart phone.
 	 * 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
 	 */
-	if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0) {
+	if (gnvs->s3u0 != 0 || gnvs->s3u1 != 0) {
 		ec_write(EC_PERIPH_CNTL_3, ec_read(EC_PERIPH_CNTL_3) | 0x00);
 		ec_write(EC_USB_S3_EN, ec_read(EC_USB_S3_EN) | 0x01);
 		printk(BIOS_DEBUG, "USB wake from S3 enabled.\n");
@@ -59,7 +59,7 @@ void mainboard_smi_sleep(u8 slp_typ)
 		 * the XHCI PME to prevent wake when the port power is cut
 		 * after the transition into suspend.
 		 */
-		if (smm_get_gnvs()->xhci) {
+		if (gnvs->xhci) {
 			u32 reg32 = pci_read_config32(PCH_XHCI_DEV, 0x74);
 			reg32 &= ~(1 << 8); /* disable PME */
 			reg32 |= (1 << 15); /* clear PME status */

src/mainboard/intel/cannonlake_rvp/smihandler.c

@@ -11,7 +11,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;

src/mainboard/intel/kblrvp/smihandler.c

@@ -15,7 +15,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;

src/mainboard/intel/kunimitsu/smihandler.c

@@ -16,7 +16,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;

src/mainboard/intel/strago/smihandler.c

@@ -23,7 +23,7 @@ int mainboard_io_trap_handler(int smif)
 	switch (smif) {
 	case 0x99:
 		printk(BIOS_DEBUG, "Sample\n");
-		smm_get_gnvs()->smif = 0;
+		gnvs->smif = 0;
 		break;
 	default:
 		return 0;
@@ -82,10 +82,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (gnvs->s3u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
+		if (gnvs->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 
@@ -95,10 +95,10 @@ void mainboard_smi_sleep(uint8_t slp_typ)
 		enable_gpe(WAKE_GPIO_EN);
 		break;
 	case ACPI_S5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (gnvs->s5u0 == 0)
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
+		if (gnvs->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
 

src/soc/intel/baytrail/smihandler.c

@@ -18,8 +18,6 @@
 #include <soc/pmc.h>
 #include <soc/nvs.h>
 
-/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs *gnvs;
 static int smm_initialized;
 
 int southbridge_io_trap_handler(int smif)
@@ -44,11 +42,6 @@ void southbridge_smi_set_eos(void)
 	enable_smi(EOS);
 }
 
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 static void busmaster_disable_on_bus(int bus)
 {
 	int slot, func;

src/soc/intel/braswell/smihandler.c

@@ -18,8 +18,6 @@
 #include <soc/gpio.h>
 #include <smmstore.h>
 
-/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs *gnvs;
 static int smm_initialized;
 
 int southbridge_io_trap_handler(int smif)
@@ -45,11 +43,6 @@ void southbridge_smi_set_eos(void)
 	enable_smi(EOS);
 }
 
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 static void busmaster_disable_on_bus(int bus)
 {
 	int slot, func;

src/soc/intel/broadwell/smihandler.c

@@ -25,16 +25,6 @@
 
 static u8 smm_initialized = 0;
 
-/*
- * GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-static struct global_nvs *gnvs;
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {

src/soc/intel/common/block/smm/smihandler.c

@@ -26,9 +26,6 @@
 #include <spi-generic.h>
 #include <stdint.h>
 
-/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs *gnvs;
-
 /* SoC overrides. */
 
 __weak const struct smm_save_state_ops *get_smm_save_state_ops(void)
@@ -125,11 +122,6 @@ void southbridge_smi_set_eos(void)
 	pmc_enable_smi(EOS);
 }
 
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 static void busmaster_disable_on_bus(int bus)
 {
 	int slot, func;

src/soc/intel/common/block/smm/smitraphandler.c

@@ -24,7 +24,6 @@
 /* Inherited from cpu/x86/smm.h resulting in a different signature */
 int southbridge_io_trap_handler(int smif)
 {
-	struct global_nvs *gnvs = smm_get_gnvs();
 	switch (smif) {
 	case 0x32:
 		printk(BIOS_DEBUG, "OS Init\n");
@@ -61,7 +60,6 @@ void smihandler_southbridge_monitor(
 	u32 data, mask = 0;
 	u8 trap_sts;
 	int i;
-	struct global_nvs *gnvs = smm_get_gnvs();
 
 	/* TRSR - Trap Status Register */
 	trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);

src/soc/intel/denverton_ns/smihandler.c

@@ -16,8 +16,6 @@
 #include <soc/pm.h>
 #include <soc/nvs.h>
 
-/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs *gnvs;
 static int smm_initialized;
 
 int southbridge_io_trap_handler(int smif)
@@ -37,9 +35,10 @@ int southbridge_io_trap_handler(int smif)
 	return 0;
 }
 
-void southbridge_smi_set_eos(void) { enable_smi(EOS); }
+void southbridge_smi_set_eos(void)
-
+{
-struct global_nvs *smm_get_gnvs(void) { return gnvs; }
+	enable_smi(EOS);
+}
 
 static void busmaster_disable_on_bus(int bus)
 {

src/southbridge/intel/bd82x6x/smihandler.c

@@ -17,12 +17,6 @@
 #include "pch.h"
 #include "nvs.h"
 
-static struct global_nvs *gnvs;
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {
@@ -186,7 +180,7 @@ void southbridge_smi_monitor(void)
 
 void southbridge_smm_xhci_sleep(u8 slp_type)
 {
-	if (smm_get_gnvs()->xhci)
+	if (gnvs->xhci)
 		xhci_sleep(slp_type);
 }
 

src/southbridge/intel/i82801gx/smihandler.c

@@ -21,9 +21,6 @@
 u16 pmbase = DEFAULT_PMBASE;
 u8 smm_initialized = 0;
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */
-struct global_nvs *gnvs = (struct global_nvs *)0x0;
-
 void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
 {
 	gnvs = *(struct global_nvs **)0x500;

src/southbridge/intel/i82801ix/smihandler.c

@@ -9,10 +9,11 @@
 
 #include "nvs.h"
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
+#if !CONFIG(SMM_TSEG)
- * by coreboot.
+/* For qemu/x86-q35 to build properly. */
- */
+struct global_nvs *gnvs;
-struct global_nvs *gnvs = (struct global_nvs *)0x0;
+#endif
+
 void *tcg = (void *)0x0;
 void *smi1 = (void *)0x0;
 

src/southbridge/intel/i82801jx/smihandler.c

@@ -15,10 +15,6 @@
 u16 pmbase = DEFAULT_PMBASE;
 u8 smm_initialized = 0;
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-struct global_nvs *gnvs = (struct global_nvs *)0x0;
 void *tcg = (void *)0x0;
 void *smi1 = (void *)0x0;
 

src/southbridge/intel/ibexpeak/smihandler.c

@@ -23,15 +23,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-static struct global_nvs *gnvs;
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {

src/southbridge/intel/lynxpoint/smihandler.c

@@ -21,15 +21,6 @@
 
 static u8 smm_initialized = 0;
 
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-static struct global_nvs *gnvs;
-struct global_nvs *smm_get_gnvs(void)
-{
-	return gnvs;
-}
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {