soc/intel/broadwell: Relocate `report_memory_config` function
This allows us to make it static, like it is on Haswell. Change-Id: I8f782ce6ac390082c56a881c6b26d82b548205d9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -19,7 +19,6 @@ void raminit(struct pei_data *pei_data);
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struct chipset_power_state;
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struct chipset_power_state;
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struct chipset_power_state *fill_power_state(void);
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struct chipset_power_state *fill_power_state(void);
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void report_platform_info(void);
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void report_platform_info(void);
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void report_memory_config(void);
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void set_max_freq(void);
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void set_max_freq(void);
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@ -21,6 +21,47 @@
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/systemagent.h>
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#include <soc/systemagent.h>
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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static void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
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i, ch_conf);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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/*
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/*
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* Find PEI executable in coreboot filesystem and execute it.
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* Find PEI executable in coreboot filesystem and execute it.
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*/
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*/
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@ -180,44 +180,3 @@ void report_platform_info(void)
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report_pch_info();
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report_pch_info();
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report_igd_info();
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report_igd_info();
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}
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}
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[2];
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int i;
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addr_decoder_common = MCHBAR32(0x5000);
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addr_decode_ch[0] = MCHBAR32(0x5004);
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addr_decode_ch[1] = MCHBAR32(0x5008);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(0x5e04) * 13333 * 2 + 50)/100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n",
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i, ch_conf);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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