diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 046fd233f4..dbb628bfff 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -63,6 +63,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SVI2 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 43ed7fed05..cebdf7c5b9 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -146,13 +146,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { - /* Voltage off for VID codes 0xF8 to 0xFF */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - - (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index fdbe47e342..79ebc7eee5 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -22,10 +22,6 @@ union pstate_msr { #define PSTATE_DEF_FREQ_DIV_MAX 0x3E #define PSTATE_DEF_CORE_FREQ_BASE 25 -/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f7583e720a..5dc846bb00 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -66,6 +66,18 @@ config SOC_AMD_COMMON_BLOCK_SMM Add common SMM relocation, finalization and handler functionality to the build. +config SOC_AMD_COMMON_BLOCK_SVI2 + bool + help + Select this option is the SoC uses the serial VID 2 standard for + encoding the voltage it requests from the VRM. + +config SOC_AMD_COMMON_BLOCK_SVI3 + bool + help + Select this option is the SoC uses the serial VID 3 standard for + encoding the voltage it requests from the VRM. + config SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H bool select COLLECT_TIMESTAMPS_NO_TSC # selected use SoC-specific timestamp function diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index bd9e8ff88f..055341ec4d 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -4,6 +4,9 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE) += update_microcode.c romstage-y += cpu.c ramstage-y += cpu.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI2) += svi2.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_SVI3) += svi3.c + ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UCODE),y) define add-ucode-as-cbfs cbfs-files-y += cpu_microcode_$(2).bin diff --git a/src/soc/amd/common/block/cpu/svi2.c b/src/soc/amd/common/block/cpu/svi2.c new file mode 100644 index 0000000000..0a41b78b26 --- /dev/null +++ b/src/soc/amd/common/block/cpu/svi2.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ +#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 +#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L + +uint32_t get_uvolts_from_vid(uint16_t core_vid) +{ + if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { + /* Voltage off for VID codes 0xF8 to 0xFF */ + return 0; + } else { + return SERIAL_VID_2_MAX_MICROVOLTS - + (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); + } +} diff --git a/src/soc/amd/common/block/cpu/svi3.c b/src/soc/amd/common/block/cpu/svi3.c new file mode 100644 index 0000000000..35a4a789de --- /dev/null +++ b/src/soc/amd/common/block/cpu/svi3.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ +#define SERIAL_VID_3_DECODE_MICROVOLTS 5000 +#define SERIAL_VID_3_BASE_MICROVOLTS 245000L + +uint32_t get_uvolts_from_vid(uint16_t core_vid) +{ + if (core_vid == 0x00) { + /* Voltage off for VID code 0x00 */ + return 0; + } else { + return SERIAL_VID_3_BASE_MICROVOLTS + + (SERIAL_VID_3_DECODE_MICROVOLTS * core_vid); + } +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h index 3501b22104..cbce028631 100644 --- a/src/soc/amd/common/block/include/amdblocks/cpu.h +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -16,6 +16,7 @@ void write_resume_eip(void); union pstate_msr; /* proper definition is in soc/msr.h */ +uint32_t get_uvolts_from_vid(uint16_t core_vid); uint32_t get_pstate_core_freq(union pstate_msr pstate_reg); uint32_t get_pstate_core_power(union pstate_msr pstate_reg); const acpi_cstate_t *get_cstate_config_data(size_t *size); diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 3ffee09d4f..5e9b7f95bb 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -69,6 +69,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_BLOCK_SMU # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SPI # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H # FIXME: This is likely incompatible select SOC_AMD_COMMON_BLOCK_UART # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_UCODE # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 37349c15ae..b9ea0eb784 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -123,13 +123,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if (core_vid == 0x00) { - /* Voltage off for VID code 0x00 */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS + - (SERIAL_VID_3_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index 7b6889709e..ad4d9d0445 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -22,10 +22,6 @@ union pstate_msr { #define PSTATE_DEF_CORE_FREQ_BASE 5 -/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ -#define SERIAL_VID_3_DECODE_MICROVOLTS 5000 -#define SERIAL_VID_3_BASE_MICROVOLTS 245000L - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 737a8dbfa8..2df289f6d2 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -71,6 +71,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_STB + select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index f6a95bf565..0574ba7627 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -148,13 +148,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if (core_vid == 0x00) { - /* Voltage off for VID code 0x00 */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS + - (SERIAL_VID_3_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index cb03425d2a..b83997a029 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -23,10 +23,6 @@ union pstate_msr { #define PSTATE_DEF_FREQ_DIV_MAX 0x3E #define PSTATE_DEF_CORE_FREQ_BASE 25 -/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ -#define SERIAL_VID_3_DECODE_MICROVOLTS 5000 -#define SERIAL_VID_3_BASE_MICROVOLTS 245000L - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index cb54306ed1..96a287cf7f 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -69,6 +69,7 @@ config SOC_AMD_PHOENIX select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SVI3 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index e3996ba869..e147e88aee 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -149,13 +149,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if (core_vid == 0x00) { - /* Voltage off for VID code 0x00 */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS + - (SERIAL_VID_3_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 8eee0683ae..173ee0999b 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -25,10 +25,6 @@ union pstate_msr { #define PSTATE_DEF_FREQ_DIV_MAX 0x3E #define PSTATE_DEF_CORE_FREQ_BASE 25 -/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */ -#define SERIAL_VID_3_DECODE_MICROVOLTS 5000 -#define SERIAL_VID_3_BASE_MICROVOLTS 245000L - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 325a65a166..746b4fb87d 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -59,6 +59,7 @@ config SOC_AMD_PICASSO select SOC_AMD_COMMON_BLOCK_SMU select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY select SOC_AMD_COMMON_BLOCK_SPI + select SOC_AMD_COMMON_BLOCK_SVI2 select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index b7d954d982..d1232e3525 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -150,13 +150,7 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg) current_divisor = pstate_reg.idd_div; /* Voltage */ - if ((core_vid >= 0xF8) && (core_vid <= 0xFF)) { - /* Voltage off for VID codes 0xF8 to 0xFF */ - voltage_in_uvolts = 0; - } else { - voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS - - (SERIAL_VID_2_DECODE_MICROVOLTS * core_vid); - } + voltage_in_uvolts = get_uvolts_from_vid(core_vid); /* Power in mW */ power_in_mw = (voltage_in_uvolts) / 10 * current_value_amps; diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 2f0237204e..0747b847e3 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -26,8 +26,4 @@ union pstate_msr { #define PSTATE_DEF_FREQ_DIV_MAX 0x3E #define PSTATE_DEF_CORE_FREQ_BASE 25 -/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */ -#define SERIAL_VID_2_DECODE_MICROVOLTS 6250 -#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L - #endif /* AMD_PICASSO_MSR_H */