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soc/intel/baytrail,broadwell: Refactor acpi_wake_source() 

Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2020-12-23 06:11:32 +02:00
parent 548d350305
commit 23b081825d
2 changed files with 11 additions and 22 deletions
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16
src/soc/intel/baytrail/ramstage.c
View File

@ -117,12 +117,13 @@ static void fill_in_pattrs(void)
} }
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void s3_save_acpi_wake_source(struct global_nvs *gnvs) static void save_acpi_wake_source(void)
{ {
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
struct global_nvs *gnvs = acpi_get_gnvs();
uint16_t pm1; uint16_t pm1;
if (!ps) if (!ps || !gnvs)
return; return;
pm1 = ps->pm1_sts & ps->pm1_en; pm1 = ps->pm1_sts & ps->pm1_en;
@ -142,14 +143,6 @@ static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
gnvs->pm1i); gnvs->pm1i);
} }
static void s3_resume_prepare(void)
{
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs && acpi_is_wakeup_s3())
s3_save_acpi_wake_source(gnvs);
}
static void baytrail_enable_2x_refresh_rate(void) static void baytrail_enable_2x_refresh_rate(void)
{ {
u32 reg; u32 reg;
@ -172,7 +165,8 @@ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
/* Indicate S3 resume to rest of ramstage. */ /* Indicate S3 resume to rest of ramstage. */
s3_resume_prepare(); if (acpi_is_wakeup_s3())
save_acpi_wake_source();
/* Run reference code. */ /* Run reference code. */
baytrail_run_reference_code(); baytrail_run_reference_code();

17
src/soc/intel/broadwell/ramstage.c
View File

@ -12,13 +12,14 @@
#include <soc/intel/broadwell/chip.h> #include <soc/intel/broadwell/chip.h>
/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ /* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */
static void save_acpi_wake_source(struct global_nvs *gnvs) static void save_acpi_wake_source(void)
{ {
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
struct global_nvs *gnvs = acpi_get_gnvs();
uint16_t pm1; uint16_t pm1;
int gpe_reg; int gpe_reg;
if (!ps) if (!ps || !gnvs)
return; return;
pm1 = ps->pm1_sts & ps->pm1_en; pm1 = ps->pm1_sts & ps->pm1_en;
@ -62,16 +63,10 @@ static void save_acpi_wake_source(struct global_nvs *gnvs)
gnvs->pm1i, gnvs->gpei); gnvs->pm1i, gnvs->gpei);
} }
static void s3_resume_prepare(void)
{
struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs && acpi_is_wakeup_s3())
save_acpi_wake_source(gnvs);
}
void broadwell_init_pre_device(void *chip_info) void broadwell_init_pre_device(void *chip_info)
{ {
s3_resume_prepare(); if (acpi_is_wakeup_s3())
save_acpi_wake_source();
broadwell_run_reference_code(); broadwell_run_reference_code();
} }