From 23ddcb0bc4a952e773cf62fefc499bbbe490f7af Mon Sep 17 00:00:00 2001
From: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Date: Fri, 1 Jul 2022 13:46:26 +0800
Subject: [PATCH] mb/google/brya: Disable PCH USB2 phy power gating for crota

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.

BUG=b:237725329
TEST=Verify the build for crota board

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
---
 src/mainboard/google/brya/variants/crota/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb
index 2e51d40331..e958b68557 100644
--- a/src/mainboard/google/brya/variants/crota/overridetree.cb
+++ b/src/mainboard/google/brya/variants/crota/overridetree.cb
@@ -29,6 +29,10 @@ chip soc/intel/alderlake
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
 	register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"
 
+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "usb2_phy_sus_pg_disable" = "1"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |