mb/google/octopus/var/fleex: Add cs42l42 HSBIAS setting

Disable HSBIAS sense setting.

BUG=b:184103445
TEST=boot to check cs42l42 is functional.

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12c0e0a0f7490d35d36fe8ccbc940f29e1bb7976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Ian Feng 2021-05-07 14:24:54 +08:00 committed by Patrick Georgi
parent 2be6da1d49
commit 23e15b1223
1 changed files with 1 additions and 0 deletions

View File

@ -148,6 +148,7 @@ chip soc/intel/apollolake
register "bias_lvls[2]" = "4"
register "bias_lvls[3]" = "1"
register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
register "hs_bias_sense_disable" = "true"
device i2c 48 on end
end
end # - I2C 5