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soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En 

Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.

BUG=🅱️146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41812
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2020-05-27 23:11:19 -07:00 committed by Furquan Shaikh
parent 74b1919f17
commit 23e8b5b494
2 changed files with 11 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/tigerlake/chip.h
View File

@ -216,10 +216,6 @@ struct soc_intel_tigerlake_config {
uint8_t TcssXhciEn;
uint8_t TcssXdciEn;
/* TCSS DMA */
uint8_t TcssDma0En;
uint8_t TcssDma1En;
/*
* IOM Port Config
* If a port orientation needs to be controlled by the SOC this setting must be

13
src/soc/intel/tigerlake/romstage/fsp_params.c
View File

@ -116,8 +116,17 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssXdciEn = config->TcssXdciEn;
/* TCSS DMA */
m_cfg->TcssDma0En = config->TcssDma0En;
m_cfg->TcssDma1En = config->TcssDma1En;
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
if (dev)
m_cfg->TcssDma0En = dev->enabled;
else
m_cfg->TcssDma0En = 0;
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
if (dev)
m_cfg->TcssDma1En = dev->enabled;
else
m_cfg->TcssDma1En = 0;
/* USB4/TBT */
dev = pcidev_path_on_root(SA_DEVFN_TBT0);