northbridge/intelsch/raminit.h: Remove a trailing whitespace
Change-Id: Ic8d6007898a08ade9d6e5947cd368b7a0545928a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6314 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
9558c00446
commit
23fa3c245a
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@ -25,51 +25,51 @@
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**/
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**/
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#define BIT(x) (1<<x)
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#define BIT(x) (1<<x)
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#define EBP_TRP_MASK (BIT(1) | BIT(0))
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#define EBP_TRP_MASK (BIT(1) | BIT(0))
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#define TRP_LOW 3h
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#define TRP_LOW 3h
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#define TRP_HIGH 5h
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#define TRP_HIGH 5h
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#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/
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#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/
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#define EBP_TRCD_MASK (BIT(3) | BIT(2))
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#define EBP_TRCD_MASK (BIT(3) | BIT(2))
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#define TRCD_LOW 3h
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#define TRCD_LOW 3h
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#define TRCD_HIGH 5h
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#define TRCD_HIGH 5h
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#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/
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#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/
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#define EBP_TCL_MASK (BIT(5) | BIT(4))
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#define EBP_TCL_MASK (BIT(5) | BIT(4))
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#define TCL_LOW 3 /* Minimum supported CL*/
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#define TCL_LOW 3 /* Minimum supported CL*/
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#define TCL_HIGH 5 /* Maximum supported CL*/
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#define TCL_HIGH 5 /* Maximum supported CL*/
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#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/
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#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/
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#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/
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#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/
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#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/
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#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/
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#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/
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#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/
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#define EBP_FREQ_MASK (BIT(10)| BIT(9))
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#define EBP_FREQ_MASK (BIT(10)| BIT(9))
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#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/
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#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/
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#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/
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#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/
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#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/
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#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/
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#define EBP_REFRESH_MASK (BIT(12)| BIT(11))
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#define EBP_REFRESH_MASK (BIT(12)| BIT(11))
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#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/
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#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/
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#define EBP_REF_DIS 00h /* Mask for refresh disabled*/
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#define EBP_REF_DIS 00h /* Mask for refresh disabled*/
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#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/
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#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/
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#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/
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#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/
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#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/
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#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/
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#define EBP_WIDTH_MASK BIT(15)
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#define EBP_WIDTH_MASK BIT(15)
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#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/
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#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/
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#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/
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#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/
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#define EBP_DENSITY_MASK (BIT(17)| BIT(16))
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#define EBP_DENSITY_MASK (BIT(17)| BIT(16))
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#define EBP_DENSITY_OFFSET 16
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#define EBP_DENSITY_OFFSET 16
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#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/
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#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/
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#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/
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#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/
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#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/
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#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/
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#define EBP_RANKS_MASK BIT(18)
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#define EBP_RANKS_MASK BIT(18)
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#define EBP_RANKS_OFFSET 18
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#define EBP_RANKS_OFFSET 18
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#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/
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#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/
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#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/
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#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/
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#define EBP_2X_MASK BIT(20)
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#define EBP_2X_MASK BIT(20)
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#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/
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#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/
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#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/
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#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/
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#define EBP_DRAM_PARM_MASK BIT(21)
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#define EBP_DRAM_PARM_MASK BIT(21)
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#define EBP_DRAM_PARM_OFFSET 21
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#define EBP_DRAM_PARM_OFFSET 21
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#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/
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#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/
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#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/
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#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/
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#define EBP_BOOT_PATH BIT(31)
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#define EBP_BOOT_PATH BIT(31)
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@ -105,35 +105,35 @@
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/* SCH Message Ports and Registers*/
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/* SCH Message Ports and Registers*/
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#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */
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#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */
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#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */
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#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */
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#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */
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#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */
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#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */
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#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */
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#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */
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#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */
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#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */
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#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */
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#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */
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#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */
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#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */
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#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */
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#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */
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#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */
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#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */
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#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */
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#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */
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#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */
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#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */
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#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */
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#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */
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#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */
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#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */
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#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */
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#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */
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#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */
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#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */
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#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */
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#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */
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#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */
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#define DTR_TCL_OFFSET 4 /* CAS latency offset */
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#define DTR_TCL_OFFSET 4 /* CAS latency offset */
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#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */
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#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */
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#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */
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#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */
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#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */
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#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */
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#define DCO_FIELDS 0xF /* Pertinent fields in DCO */
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#define DCO_FIELDS 0xF /* Pertinent fields in DCO */
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#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */
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#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */
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#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */
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#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */
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#define DCO_IC BIT(7) /* Initialization complete bit */
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#define DCO_IC BIT(7) /* Initialization complete bit */
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#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */
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#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */
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#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */
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#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */
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#define SCH_MSG_TEST_PORT 05h /* Test port */
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#define SCH_MSG_TEST_PORT 05h /* Test port */
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#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */
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#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */
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/* Jedec initialization mapping into the MDR address field for DRAM init messages*/
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/* Jedec initialization mapping into the MDR address field for DRAM init messages*/
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