intel/amenia: Update eMMC DLL settings
Update eMMC DLL setting for amenia board, after that system can boot up with eMMC successfully. BUG=chrome-os-partner:51844 TEST=Boot up with eMMC Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -7,11 +7,31 @@ chip soc/intel/apollolake
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register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
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register "pcie_rp0_clkreq_pin" = "3" # wifi/bt
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register "pcie_rp2_clkreq_pin" = "0" # SSD
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register "pcie_rp2_clkreq_pin" = "0" # SSD
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# EMMC TX DATA Delay 1#
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# eMMC TX DATA Delay 1#
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# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
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# 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400
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# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
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# 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200
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register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
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register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
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# eMMC TX DATA Delay 2#
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# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
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# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
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# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
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# 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode
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register "emmc_tx_data_cntl2" = "0x1c1c1c00"
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# eMMC RX CMD/DATA Delay 1#
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# 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50
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# 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50
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# 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50
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# 0x00[6:0] stands for 0 delay for SDR12/Compatibility
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register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00"
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# eMMC RX CMD/DATA Delay 2#
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# 0x01[17:16] stands for Rx Clock before Output Buffer
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# 0x00[14:8] stands for 0 delay for Auto Tuning Mode
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# 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200
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register "emmc_rx_cmd_data_cntl2" = "0x1001c"
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# LPSS S0ix Enable
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# LPSS S0ix Enable
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register "lpss_s0ix_enable" = "1"
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register "lpss_s0ix_enable" = "1"
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