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usbdebug: Change debug port scanning 

On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
all physical ports one after other in incrementing order. To avoid
possible problems with other USB devices, one can select the port
number here and bypass the scan.

Intel platforms can communicate with usbdebug dongle on one
physical port only, and this option makes no difference there.

Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki 2013-08-12 20:40:37 +03:00
parent f7381f8cd1
commit 2410010018
12 changed files with 24 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/console/Kconfig
View File

@ -145,9 +145,6 @@ config SPKMODEM
config HAVE_USBDEBUG
def_bool n
config USBDEBUG
def_bool n
config USBDEBUG
bool "USB 2.0 EHCI debug dongle support"
default n
@ -169,25 +166,21 @@ config USBDEBUG
If unsure, say N.
# Note: This option doesn't make sense on Intel ICH / AMD SB600 southbridges
# as those hardcode the physical USB port to be used as Debug Port to 1.
# It cannot be changed by coreboot.
config USBDEBUG_DEFAULT_PORT
int "Default USB port to use as Debug Port"
default 1
depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
default 0
depends on USBDEBUG
help
This option selects which physical USB port coreboot will try to
use as EHCI Debug Port first (valid values are: 1-15).
Selects which physical USB port usbdebug dongle is connected to.
Setting of 0 means to scan possible ports starting from 1.
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
it will try all the other ports one after the other. This will take
a few seconds of time though, and thus slow down the booting process.
Intel platforms have hardwired the debug port location and this
setting makes no difference there.
Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number (1-15) refers to which
actual port on your mainboard (potentially also USB pin headers
on your mainboard) is highly board-specific, and you'll likely
your boot time. Which USB port number refers to which actual
port on your mainboard (potentially also USB pin headers on
your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.
# TODO: Deps?

19
src/lib/usbdebug.c
View File

@ -421,8 +421,13 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_
HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase)));
ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset);
info->ehci_debug = (void *)0;
memset(&info->ep_pipe, 0, sizeof (info->ep_pipe));
if (CONFIG_USBDEBUG_DEFAULT_PORT > 0)
set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT);
else
set_debug_port(1);
try_next_time:
port_map_tried = 0;
@ -630,6 +635,7 @@ err:
//return ret;
next_debug_port:
#if CONFIG_USBDEBUG_DEFAULT_PORT==0
port_map_tried |= (1 << (debug_port - 1));
new_debug_port = ((debug_port-1 + 1) % n_ports) + 1;
if (port_map_tried != ((1 << n_ports) - 1)) {
@ -637,10 +643,15 @@ next_debug_port:
goto try_next_port;
}
if (--playtimes) {
//set_debug_port(new_debug_port);
set_debug_port(debug_port);
set_debug_port(new_debug_port);
goto try_next_time;
}
#else
if (0)
goto try_next_port;
if (--playtimes)
goto try_next_time;
#endif
return -10;
}
@ -774,7 +785,7 @@ int usbdebug_init(void)
struct ehci_debug_info *dbg_info = dbgp_ehci_info();
#if defined(__PRE_RAM__) || !CONFIG_EARLY_CONSOLE
enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
enable_usbdebug(0);
#endif
return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
}

1
src/southbridge/amd/agesa/hudson/enable_usbdebug.c
View File

@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port)
EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2),
PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
set_debug_port(port);
}

4
src/southbridge/amd/sb600/Kconfig
View File

@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xe0
config USBDEBUG_DEFAULT_PORT
int
default 0
choice
prompt "SATA Mode"
default SATA_MODE_IDE

3
src/southbridge/amd/sb600/enable_usbdebug.c
View File

@ -36,9 +36,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, 0x13, 5); /* USB EHCI, D19:F5 */
/* Select the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port);
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

5
src/southbridge/amd/sb700/enable_usbdebug.c
View File

@ -58,9 +58,4 @@ void enable_usbdebug(unsigned int port)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/*
* Select the requested physical USB port (1-15) as the Debug Port.
* Must be called after the EHCI BAR has been set up (see above).
*/
set_debug_port(port);
}

1
src/southbridge/amd/sb800/enable_usbdebug.c
View File

@ -57,5 +57,4 @@ void enable_usbdebug(unsigned int port)
EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2),
PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
set_debug_port(port);
}

4
src/southbridge/intel/i82801gx/Kconfig
View File

@ -36,10 +36,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xa0
config USBDEBUG_DEFAULT_PORT
int
default 1
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801gx/bootblock.c"

4
src/southbridge/intel/i82801ix/Kconfig
View File

@ -37,10 +37,6 @@ config EHCI_DEBUG_OFFSET
hex
default 0xa0
config USBDEBUG_DEFAULT_PORT
int
default 1
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801ix/bootblock.c"

3
src/southbridge/nvidia/ck804/enable_usbdebug.c
View File

@ -52,9 +52,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, CK804_DEVN_BASE + 2, 1); /* USB EHCI */
/* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port);
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

3
src/southbridge/nvidia/mcp55/enable_usbdebug.c
View File

@ -46,9 +46,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 2, 1); /* USB EHCI */
/* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port);
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);

3
src/southbridge/sis/sis966/enable_usbdebug.c
View File

@ -48,9 +48,6 @@ void enable_usbdebug(unsigned int port)
{
pci_devfn_t dev = PCI_DEV(0, SIS966_DEVN_BASE + 2, 1); /* USB EHCI */
/* Mark the requested physical USB port (1-15) as the Debug Port. */
set_debug_port(port);
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);